367 static int i5100_rank_to_slot(const struct mem_ctl_info *mci,  in i5100_rank_to_slot()  argument
370 	const struct i5100_priv *priv = mci->pvt_info;  in i5100_rank_to_slot()
421 static int i5100_csrow_to_rank(const struct mem_ctl_info *mci, int csrow)  in i5100_csrow_to_rank()  argument
423 	const struct i5100_priv *priv = mci->pvt_info;  in i5100_csrow_to_rank()
429 static int i5100_csrow_to_chan(const struct mem_ctl_info *mci, int csrow)  in i5100_csrow_to_chan()  argument
431 	const struct i5100_priv *priv = mci->pvt_info;  in i5100_csrow_to_chan()
436 static void i5100_handle_ce(struct mem_ctl_info *mci,  in i5100_handle_ce()  argument
452 	edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,  in i5100_handle_ce()
458 static void i5100_handle_ue(struct mem_ctl_info *mci,  in i5100_handle_ue()  argument
474 	edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,  in i5100_handle_ue()
480 static void i5100_read_log(struct mem_ctl_info *mci, int chan,  in i5100_read_log()  argument
483 	struct i5100_priv *priv = mci->pvt_info;  in i5100_read_log()
523 		i5100_handle_ce(mci, chan, bank, rank, syndrome, cas, ras, msg);  in i5100_read_log()
545 		i5100_handle_ue(mci, chan, bank, rank, syndrome, cas, ras, msg);  in i5100_read_log()
551 static void i5100_check_error(struct mem_ctl_info *mci)  in i5100_check_error()  argument
553 	struct i5100_priv *priv = mci->pvt_info;  in i5100_check_error()
561 		i5100_read_log(mci, i5100_ferr_nf_mem_chan_indx(dw),  in i5100_check_error()
605 static int i5100_set_scrub_rate(struct mem_ctl_info *mci, u32 bandwidth)  in i5100_set_scrub_rate()  argument
607 	struct i5100_priv *priv = mci->pvt_info;  in i5100_set_scrub_rate()
630 static int i5100_get_scrub_rate(struct mem_ctl_info *mci)  in i5100_get_scrub_rate()  argument
632 	struct i5100_priv *priv = mci->pvt_info;  in i5100_get_scrub_rate()
659 static unsigned long i5100_npages(struct mem_ctl_info *mci, int csrow)  in i5100_npages()  argument
661 	struct i5100_priv *priv = mci->pvt_info;  in i5100_npages()
662 	const unsigned chan_rank = i5100_csrow_to_rank(mci, csrow);  in i5100_npages()
663 	const unsigned chan = i5100_csrow_to_chan(mci, csrow);  in i5100_npages()
680 static void i5100_init_mtr(struct mem_ctl_info *mci)  in i5100_init_mtr()  argument
682 	struct i5100_priv *priv = mci->pvt_info;  in i5100_init_mtr()
712 static int i5100_read_spd_byte(const struct mem_ctl_info *mci,  in i5100_read_spd_byte()  argument
715 	struct i5100_priv *priv = mci->pvt_info;  in i5100_read_spd_byte()
752 static void i5100_init_dimm_csmap(struct mem_ctl_info *mci)  in i5100_init_dimm_csmap()  argument
754 	struct i5100_priv *priv = mci->pvt_info;  in i5100_init_dimm_csmap()
783 				   struct mem_ctl_info *mci)  in i5100_init_dimm_layout()  argument
785 	struct i5100_priv *priv = mci->pvt_info;  in i5100_init_dimm_layout()
794 			if (i5100_read_spd_byte(mci, i, j, 5, &rank) < 0)  in i5100_init_dimm_layout()
801 	i5100_init_dimm_csmap(mci);  in i5100_init_dimm_layout()
805 				    struct mem_ctl_info *mci)  in i5100_init_interleaving()  argument
809 	struct i5100_priv *priv = mci->pvt_info;  in i5100_init_interleaving()
847 	i5100_init_mtr(mci);  in i5100_init_interleaving()
850 static void i5100_init_csrows(struct mem_ctl_info *mci)  in i5100_init_csrows()  argument
853 	struct i5100_priv *priv = mci->pvt_info;  in i5100_init_csrows()
855 	for (i = 0; i < mci->tot_dimms; i++) {  in i5100_init_csrows()
857 		const unsigned long npages = i5100_npages(mci, i);  in i5100_init_csrows()
858 		const unsigned chan = i5100_csrow_to_chan(mci, i);  in i5100_init_csrows()
859 		const unsigned rank = i5100_csrow_to_rank(mci, i);  in i5100_init_csrows()
864 		dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers,  in i5100_init_csrows()
874 			 i5100_rank_to_slot(mci, chan, rank));  in i5100_init_csrows()
885 static void i5100_do_inject(struct mem_ctl_info *mci)  in i5100_do_inject()  argument
887 	struct i5100_priv *priv = mci->pvt_info;  in i5100_do_inject()
950 	struct mem_ctl_info *mci = to_mci(dev);  in inject_enable_write()  local
952 	i5100_do_inject(mci);  in inject_enable_write()
963 static int i5100_setup_debugfs(struct mem_ctl_info *mci)  in i5100_setup_debugfs()  argument
965 	struct i5100_priv *priv = mci->pvt_info;  in i5100_setup_debugfs()
970 	priv->debugfs = edac_debugfs_create_dir_at(mci->bus->name, i5100_debugfs);  in i5100_setup_debugfs()
988 				&mci->dev, &i5100_inject_enable_fops);  in i5100_setup_debugfs()
997 	struct mem_ctl_info *mci;  in i5100_init_one()  local
1065 	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,  in i5100_init_one()
1067 	if (!mci) {  in i5100_init_one()
1088 	mci->pdev = &pdev->dev;  in i5100_init_one()
1090 	priv = mci->pvt_info;  in i5100_init_one()
1107 	i5100_init_dimm_layout(pdev, mci);  in i5100_init_one()
1108 	i5100_init_interleaving(pdev, mci);  in i5100_init_one()
1110 	mci->mtype_cap = MEM_FLAG_FB_DDR2;  in i5100_init_one()
1111 	mci->edac_ctl_cap = EDAC_FLAG_SECDED;  in i5100_init_one()
1112 	mci->edac_cap = EDAC_FLAG_SECDED;  in i5100_init_one()
1113 	mci->mod_name = "i5100_edac.c";  in i5100_init_one()
1114 	mci->mod_ver = "not versioned";  in i5100_init_one()
1115 	mci->ctl_name = "i5100";  in i5100_init_one()
1116 	mci->dev_name = pci_name(pdev);  in i5100_init_one()
1117 	mci->ctl_page_to_phys = NULL;  in i5100_init_one()
1119 	mci->edac_check = i5100_check_error;  in i5100_init_one()
1120 	mci->set_sdram_scrub_rate = i5100_set_scrub_rate;  in i5100_init_one()
1121 	mci->get_sdram_scrub_rate = i5100_get_scrub_rate;  in i5100_init_one()
1130 	i5100_init_csrows(mci);  in i5100_init_one()
1142 	if (edac_mc_add_mc(mci)) {  in i5100_init_one()
1147 	i5100_setup_debugfs(mci);  in i5100_init_one()
1154 	edac_mc_free(mci);  in i5100_init_one()
1183 	struct mem_ctl_info *mci;  in i5100_remove_one()  local
1186 	mci = edac_mc_del_mc(&pdev->dev);  in i5100_remove_one()
1188 	if (!mci)  in i5100_remove_one()
1191 	priv = mci->pvt_info;  in i5100_remove_one()
1206 	edac_mc_free(mci);  in i5100_remove_one()