50 static int edac_pci_read_dword(struct pci_dev *dev, int reg, u32 *val32)  in edac_pci_read_dword()  argument
54 	ret = pci_read_config_dword(dev, reg, val32);  in edac_pci_read_dword()
72 static void edac_pci_write_dword(struct pci_dev *dev, int reg, u32 val32)  in edac_pci_write_dword()  argument
76 	ret = pci_write_config_dword(dev, reg, val32);  in edac_pci_write_dword()
100 	u32 val32;  in amd8111_pci_bridge_init()  local
106 	edac_pci_read_dword(dev, REG_PCI_STSCMD, &val32);  in amd8111_pci_bridge_init()
107 	if (val32 & PCI_STSCMD_CLEAR_MASK)  in amd8111_pci_bridge_init()
108 		edac_pci_write_dword(dev, REG_PCI_STSCMD, val32);  in amd8111_pci_bridge_init()
111 	edac_pci_read_dword(dev, REG_HT_LINK, &val32);  in amd8111_pci_bridge_init()
112 	if (val32 & HT_LINK_CLEAR_MASK)  in amd8111_pci_bridge_init()
113 		edac_pci_write_dword(dev, REG_HT_LINK, val32);  in amd8111_pci_bridge_init()
118 	edac_pci_read_dword(dev, REG_MEM_LIM, &val32);  in amd8111_pci_bridge_init()
119 	if (val32 & MEM_LIMIT_CLEAR_MASK)  in amd8111_pci_bridge_init()
120 		edac_pci_write_dword(dev, REG_MEM_LIM, val32);  in amd8111_pci_bridge_init()
123 	edac_pci_read_dword(dev, REG_PCI_INTBRG_CTRL, &val32);  in amd8111_pci_bridge_init()
124 	if (val32 & PCI_INTBRG_CTRL_CLEAR_MASK)  in amd8111_pci_bridge_init()
125 		edac_pci_write_dword(dev, REG_PCI_INTBRG_CTRL, val32);  in amd8111_pci_bridge_init()
130 		edac_pci_read_dword(dev, REG_PCI_STSCMD, &val32);  in amd8111_pci_bridge_init()
131 		val32 |= PCI_STSCMD_SERREN;  in amd8111_pci_bridge_init()
132 		edac_pci_write_dword(dev, REG_PCI_STSCMD, val32);  in amd8111_pci_bridge_init()
135 		edac_pci_read_dword(dev, REG_HT_LINK, &val32);  in amd8111_pci_bridge_init()
136 		val32 |= HT_LINK_CRCFEN;  in amd8111_pci_bridge_init()
137 		edac_pci_write_dword(dev, REG_HT_LINK, val32);  in amd8111_pci_bridge_init()
140 		edac_pci_read_dword(dev, REG_PCI_INTBRG_CTRL, &val32);  in amd8111_pci_bridge_init()
141 		val32 |= PCI_INTBRG_CTRL_POLL_MASK;  in amd8111_pci_bridge_init()
142 		edac_pci_write_dword(dev, REG_PCI_INTBRG_CTRL, val32);  in amd8111_pci_bridge_init()
148 	u32 val32;  in amd8111_pci_bridge_exit()  local
153 		edac_pci_read_dword(dev, REG_PCI_STSCMD, &val32);  in amd8111_pci_bridge_exit()
154 		val32 &= ~PCI_STSCMD_SERREN;  in amd8111_pci_bridge_exit()
155 		edac_pci_write_dword(dev, REG_PCI_STSCMD, val32);  in amd8111_pci_bridge_exit()
158 		edac_pci_read_dword(dev, REG_HT_LINK, &val32);  in amd8111_pci_bridge_exit()
159 		val32 &= ~HT_LINK_CRCFEN;  in amd8111_pci_bridge_exit()
160 		edac_pci_write_dword(dev, REG_HT_LINK, val32);  in amd8111_pci_bridge_exit()
163 		edac_pci_read_dword(dev, REG_PCI_INTBRG_CTRL, &val32);  in amd8111_pci_bridge_exit()
164 		val32 &= ~PCI_INTBRG_CTRL_POLL_MASK;  in amd8111_pci_bridge_exit()
165 		edac_pci_write_dword(dev, REG_PCI_INTBRG_CTRL, val32);  in amd8111_pci_bridge_exit()
173 	u32 val32;  in amd8111_pci_bridge_check()  local
176 	edac_pci_read_dword(dev, REG_PCI_STSCMD, &val32);  in amd8111_pci_bridge_check()
177 	if (val32 & PCI_STSCMD_CLEAR_MASK) {  in amd8111_pci_bridge_check()
181 			(val32 & PCI_STSCMD_SSE) != 0,  in amd8111_pci_bridge_check()
182 			(val32 & PCI_STSCMD_RMA) != 0,  in amd8111_pci_bridge_check()
183 			(val32 & PCI_STSCMD_RTA) != 0);  in amd8111_pci_bridge_check()
185 		val32 |= PCI_STSCMD_CLEAR_MASK;  in amd8111_pci_bridge_check()
186 		edac_pci_write_dword(dev, REG_PCI_STSCMD, val32);  in amd8111_pci_bridge_check()
192 	edac_pci_read_dword(dev, REG_HT_LINK, &val32);  in amd8111_pci_bridge_check()
193 	if (val32 & HT_LINK_LKFAIL) {  in amd8111_pci_bridge_check()
197 			(val32 & HT_LINK_LKFAIL) != 0);  in amd8111_pci_bridge_check()
199 		val32 |= HT_LINK_LKFAIL;  in amd8111_pci_bridge_check()
200 		edac_pci_write_dword(dev, REG_HT_LINK, val32);  in amd8111_pci_bridge_check()
206 	edac_pci_read_dword(dev, REG_PCI_INTBRG_CTRL, &val32);  in amd8111_pci_bridge_check()
207 	if (val32 & PCI_INTBRG_CTRL_DTSTAT) {  in amd8111_pci_bridge_check()
211 			(val32 & PCI_INTBRG_CTRL_DTSTAT) != 0);  in amd8111_pci_bridge_check()
213 		val32 |= PCI_INTBRG_CTRL_DTSTAT;  in amd8111_pci_bridge_check()
214 		edac_pci_write_dword(dev, REG_PCI_INTBRG_CTRL, val32);  in amd8111_pci_bridge_check()
220 	edac_pci_read_dword(dev, REG_MEM_LIM, &val32);  in amd8111_pci_bridge_check()
221 	if (val32 & MEM_LIMIT_CLEAR_MASK) {  in amd8111_pci_bridge_check()
227 			(val32 & MEM_LIMIT_DPE)  != 0,  in amd8111_pci_bridge_check()
228 			(val32 & MEM_LIMIT_RSE)  != 0,  in amd8111_pci_bridge_check()
229 			(val32 & MEM_LIMIT_RMA)  != 0,  in amd8111_pci_bridge_check()
230 			(val32 & MEM_LIMIT_RTA)  != 0,  in amd8111_pci_bridge_check()
231 			(val32 & MEM_LIMIT_STA)  != 0,  in amd8111_pci_bridge_check()
232 			(val32 & MEM_LIMIT_MDPE) != 0);  in amd8111_pci_bridge_check()
234 		val32 |= MEM_LIMIT_CLEAR_MASK;  in amd8111_pci_bridge_check()
235 		edac_pci_write_dword(dev, REG_MEM_LIM, val32);  in amd8111_pci_bridge_check()