118 	switch (pvt->fam) {  in amd64_read_dct_pci_cfg()
204 	if (pvt->fam == 0x15 && pvt->model == 0x60) {  in __set_scrub_rate()
224 	if (pvt->fam == 0xf)  in set_scrub_rate()
227 	if (pvt->fam == 0x15) {  in set_scrub_rate()
244 	if (pvt->fam == 0x15) {  in get_scrub_rate()
364 	if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) {  in get_cs_base_and_mask()
375 	} else if (pvt->fam == 0x16 ||  in get_cs_base_and_mask()
376 		  (pvt->fam == 0x15 && pvt->model >= 0x30)) {  in get_cs_base_and_mask()
397 		if (pvt->fam == 0x15)  in get_cs_base_and_mask()
479 	if (pvt->fam == 0xf && pvt->ext_model < K8_REV_E) {  in amd64_get_dram_hole_info()
486 	if (pvt->fam >= 0x10 && !dhar_mem_hoist_valid(pvt)) {  in amd64_get_dram_hole_info()
518 	*hole_offset = (pvt->fam > 0xf) ? f10_dhar_offset(pvt)  in amd64_get_dram_hole_info()
693 	bit = (pvt->fam > 0xf || pvt->ext_model >= K8_REV_F)  in determine_edac_cap()
726 	if (pvt->fam == 0x10)  in debug_dump_dramcfg_low()
755 		 (pvt->fam == 0xf) ? k8_dhar_offset(pvt)  in dump_misc_regs()
763 	if (pvt->fam == 0xf)  in dump_misc_regs()
780 	if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) {  in prep_chip_selects()
783 	} else if (pvt->fam == 0x15 && pvt->model == 0x30) {  in prep_chip_selects()
811 		if (pvt->fam == 0xf)  in read_dct_base_mask()
816 				 cs, *base1, (pvt->fam == 0x10) ? reg1  in read_dct_base_mask()
830 		if (pvt->fam == 0xf)  in read_dct_base_mask()
835 				 cs, *mask1, (pvt->fam == 0x10) ? reg1  in read_dct_base_mask()
844 	switch (pvt->fam) {  in determine_memory_type()
890 		WARN(1, KERN_ERR "%s: Family??? 0x%x\n", __func__, pvt->fam);  in determine_memory_type()
932 	if (pvt->fam == 0xf) {  in get_error_address()
942 	if (pvt->fam == 0x15) {  in get_error_address()
1010 	if (pvt->fam == 0xf)  in read_dram_base_limit_regs()
1020 	if (pvt->fam != 0x15)  in read_dram_base_limit_regs()
1181 	if (pvt->fam == 0x10 && (pvt->dclr0 & WIDTH_128))  in f1x_early_channel_count()
1348 	if (pvt->fam == 0xf)  in read_dram_ctl_register()
1555 			if (pvt->fam == 0x15 && pvt->model >= 0x30) {  in f1x_lookup_addr_in_dct()
1577 	if (pvt->fam == 0x10) {  in f1x_swap_interleaved_region()
1813 		if (pvt->fam == 0x15 && pvt->model >= 0x30)  in f1x_translate_sysaddr_to_cs()
1868 	if (pvt->fam == 0xf) {  in debug_display_dimm_sizes()
1876 	if (pvt->fam == 0x10) {  in debug_display_dimm_sizes()
2340 	if (pvt->fam >= 0x10) {  in read_mc_regs()
2343 		if (pvt->fam != 0x16)  in read_mc_regs()
2347 		if ((pvt->fam > 0x10 || pvt->model > 7) && tmp & BIT(25))  in read_mc_regs()
2441 		if (pvt->fam != 0xf)  in init_csrows()
2459 		if (pvt->fam != 0xf && row_dct1) {  in init_csrows()
2685 				 struct amd64_family_type *fam)  in setup_mci_misc_attrs()  argument
2701 	mci->ctl_name		= fam->ctl_name;  in setup_mci_misc_attrs()
2720 	pvt->fam	= boot_cpu_data.x86;  in per_family_init()
2722 	switch (pvt->fam) {  in per_family_init()
2764 		     (pvt->fam == 0xf ?  in per_family_init()