348 	edac_dbg(2, "sys_addr 0x%lx doesn't match any node\n",  in find_mc_by_sys_addr()
444 			edac_dbg(2, "InputAddr 0x%lx matches csrow %d (node %d)\n",  in input_addr_to_csrow()
451 	edac_dbg(2, "no matching csrow for InputAddr 0x%lx (MC node %d)\n",  in input_addr_to_csrow()
480 		edac_dbg(1, "  revision %d for node %d does not support DHAR\n",  in amd64_get_dram_hole_info()
487 		edac_dbg(1, "  Dram Memory Hoisting is DISABLED on this system\n");  in amd64_get_dram_hole_info()
492 		edac_dbg(1, "  Dram Memory Hoisting is DISABLED on this node %d\n",  in amd64_get_dram_hole_info()
521 	edac_dbg(1, "  DHAR info for node %d base 0x%lx offset 0x%lx size 0x%lx\n",  in amd64_get_dram_hole_info()
574 			edac_dbg(2, "using DHAR to translate SysAddr 0x%lx to DramAddr 0x%lx\n",  in sys_addr_to_dram_addr()
593 	edac_dbg(2, "using DRAM Base register to translate SysAddr 0x%lx to DramAddr 0x%lx\n",  in sys_addr_to_dram_addr()
630 	edac_dbg(2, "  Intlv Shift=%d DramAddr=0x%lx maps to InputAddr=0x%lx\n",  in dram_addr_to_input_addr()
648 	edac_dbg(2, "SysAdddr 0x%lx translates to InputAddr 0x%lx\n",  in sys_addr_to_input_addr()
707 	edac_dbg(1, "F2x%d90 (DRAM Cfg Low): 0x%08x\n", chan, dclr);  in debug_dump_dramcfg_low()
716 		edac_dbg(1, " LRDIMM %dx rank multiply\n", (dcsm & 0x3));  in debug_dump_dramcfg_low()
719 	edac_dbg(1, "All DIMMs support ECC:%s\n",  in debug_dump_dramcfg_low()
723 	edac_dbg(1, "  PAR/ERR parity: %s\n",  in debug_dump_dramcfg_low()
727 		edac_dbg(1, "  DCT 128bit mode width: %s\n",  in debug_dump_dramcfg_low()
730 	edac_dbg(1, "  x4 logical DIMMs present: L0: %s L1: %s L2: %s L3: %s\n",  in debug_dump_dramcfg_low()
740 	edac_dbg(1, "F3xE8 (NB Cap): 0x%08x\n", pvt->nbcap);  in dump_misc_regs()
742 	edac_dbg(1, "  NB two channel DRAM capable: %s\n",  in dump_misc_regs()
745 	edac_dbg(1, "  ECC capable: %s, ChipKill ECC capable: %s\n",  in dump_misc_regs()
751 	edac_dbg(1, "F3xB0 (Online Spare): 0x%08x\n", pvt->online_spare);  in dump_misc_regs()
753 	edac_dbg(1, "F1xF0 (DRAM Hole Address): 0x%08x, base: 0x%08x, offset: 0x%08x\n",  in dump_misc_regs()
758 	edac_dbg(1, "  DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no");  in dump_misc_regs()
808 			edac_dbg(0, "  DCSB0[%d]=0x%08x reg: F2x%x\n",  in read_dct_base_mask()
815 			edac_dbg(0, "  DCSB1[%d]=0x%08x reg: F2x%x\n",  in read_dct_base_mask()
827 			edac_dbg(0, "    DCSM0[%d]=0x%08x reg: F2x%x\n",  in read_dct_base_mask()
834 			edac_dbg(0, "    DCSM1[%d]=0x%08x reg: F2x%x\n",  in read_dct_base_mask()
1192 	edac_dbg(0, "Data width is not 128 bits - need more decoding\n");  in f1x_early_channel_count()
1352 		edac_dbg(0, "F2x110 (DCTSelLow): 0x%08x, High range addrs at: 0x%x\n",  in read_dram_ctl_register()
1355 		edac_dbg(0, "  DCTs operate in %s mode\n",  in read_dram_ctl_register()
1359 			edac_dbg(0, "  Address range split per DCT: %s\n",  in read_dram_ctl_register()
1362 		edac_dbg(0, "  data interleave for ECC: %s, DRAM cleared since last warm reset: %s\n",  in read_dram_ctl_register()
1366 		edac_dbg(0, "  channel interleave: %s, "  in read_dram_ctl_register()
1538 	edac_dbg(1, "input addr: 0x%llx, DCT: %d\n", in_addr, dct);  in f1x_lookup_addr_in_dct()
1546 		edac_dbg(1, "    CSROW=%d CSBase=0x%llx CSMask=0x%llx\n",  in f1x_lookup_addr_in_dct()
1551 		edac_dbg(1, "    (InputAddr & ~CSMask)=0x%llx (CSBase & ~CSMask)=0x%llx\n",  in f1x_lookup_addr_in_dct()
1561 			edac_dbg(1, " MATCH csrow=%d\n", cs_found);  in f1x_lookup_addr_in_dct()
1616 	edac_dbg(1, "(range %d) SystemAddr= 0x%llx Limit=0x%llx\n",  in f1x_match_to_this_node()
1673 	edac_dbg(1, "   Normalized DCT addr: 0x%llx\n", chan_addr);  in f1x_match_to_this_node()
1704 	edac_dbg(1, "(range %d) SystemAddr= 0x%llx Limit=0x%llx\n",  in f15_m30h_match_to_this_node()
1782 	edac_dbg(1, "   Normalized DCT addr: 0x%llx\n", chan_addr);  in f15_m30h_match_to_this_node()
1886 	edac_dbg(1, "F2x%d80 (DRAM Bank Address Mapping): 0x%08x\n",  in debug_display_dimm_sizes()
2090 	edac_dbg(0, "syndrome(%x) not found\n", syndrome);  in decode_syndrome()
2256 	edac_dbg(1, "F1: %s\n", pci_name(pvt->F1));  in reserve_mc_sibling_devs()
2257 	edac_dbg(1, "F2: %s\n", pci_name(pvt->F2));  in reserve_mc_sibling_devs()
2258 	edac_dbg(1, "F3: %s\n", pci_name(pvt->F3));  in reserve_mc_sibling_devs()
2284 	edac_dbg(0, "  TOP_MEM:  0x%016llx\n", pvt->top_mem);  in read_mc_regs()
2290 		edac_dbg(0, "  TOP_MEM2: 0x%016llx\n", pvt->top_mem2);  in read_mc_regs()
2292 		edac_dbg(0, "  TOP_MEM2 disabled\n");  in read_mc_regs()
2308 		edac_dbg(1, "  DRAM range[%d], base: 0x%016llx; limit: 0x%016llx\n",  in read_mc_regs()
2313 		edac_dbg(1, "   IntlvEn=%s; Range access: %s%s IntlvSel=%d DstNode=%d\n",  in read_mc_regs()
2338 	edac_dbg(1, "  DIMM type: %s\n", edac_mem_types[pvt->dram_type]);  in read_mc_regs()
2405 	edac_dbg(0, "csrow: %d, channel: %d, DBAM idx: %d\n",  in get_csrow_nr_pages()
2407 	edac_dbg(0, "nr_pages/channel: %u\n", nr_pages);  in get_csrow_nr_pages()
2430 	edac_dbg(0, "node %d, NBCFG=0x%08x[ChipKillEccCap: %d|DramEccEn: %d]\n",  in init_csrows()
2450 		edac_dbg(1, "MC node: %d, csrow: %d\n",  in init_csrows()
2466 		edac_dbg(1, "Total csrow%d pages: %u\n", i, nr_pages);  in init_csrows()
2517 		edac_dbg(0, "core: %u, MCG_CTL: 0x%llx, NB MSR is %s\n",  in nb_mce_bank_enabled_on_node()
2590 	edac_dbg(0, "1: node %d, NBCFG=0x%08x[DramEccEn: %d]\n",  in enable_ecc_error_reporting()
2615 	edac_dbg(0, "2: node %d, NBCFG=0x%08x[DramEccEn: %d]\n",  in enable_ecc_error_reporting()
2848 		edac_dbg(1, "failed edac_mc_add_mc()\n");  in init_one_instance()
2885 		edac_dbg(0, "ret=%d\n", ret);  in probe_one_instance()