365 		csbase		= pvt->csels[dct].csbases[csrow];  in get_cs_base_and_mask()
366 		csmask		= pvt->csels[dct].csmasks[csrow];  in get_cs_base_and_mask()
377 		csbase          = pvt->csels[dct].csbases[csrow];  in get_cs_base_and_mask()
378 		csmask          = pvt->csels[dct].csmasks[csrow >> 1];  in get_cs_base_and_mask()
393 		csbase		= pvt->csels[dct].csbases[csrow];  in get_cs_base_and_mask()
394 		csmask		= pvt->csels[dct].csmasks[csrow >> 1];  in get_cs_base_and_mask()
415 	for (i = 0; i < pvt->csels[dct].b_cnt; i++)
418 	pvt->csels[dct].csbases[i]
421 	for (i = 0; i < pvt->csels[dct].m_cnt; i++)
710 		u32 dcsm = pvt->csels[chan].csmasks[0];  in debug_dump_dramcfg_low()
781 		pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8;  in prep_chip_selects()
782 		pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 8;  in prep_chip_selects()
784 		pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 4;  in prep_chip_selects()
785 		pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 2;  in prep_chip_selects()
787 		pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8;  in prep_chip_selects()
788 		pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 4;  in prep_chip_selects()
804 		u32 *base0 = &pvt->csels[0].csbases[cs];  in read_dct_base_mask()
805 		u32 *base1 = &pvt->csels[1].csbases[cs];  in read_dct_base_mask()
823 		u32 *mask0 = &pvt->csels[0].csmasks[cs];  in read_dct_base_mask()
824 		u32 *mask1 = &pvt->csels[1].csmasks[cs];  in read_dct_base_mask()
873 		dcsm = pvt->csels[0].csmasks[0];  in determine_memory_type()
1304 	u32 dcsm = pvt->csels[dct].csmasks[cs_mask_nr];  in f15_m60h_dbam_to_chip_select()
1865 	u32 *dcsb = ctrl ? pvt->csels[1].csbases : pvt->csels[0].csbases;  in debug_display_dimm_sizes()
1880 				 pvt->csels[1].csbases :  in debug_display_dimm_sizes()
1881 				 pvt->csels[0].csbases;  in debug_display_dimm_sizes()
1884 		dcsb = pvt->csels[1].csbases;  in debug_display_dimm_sizes()
2822 	layers[0].size = pvt->csels[0].b_cnt;  in init_one_instance()