Lines Matching refs:and

4 #	Licensed and distributed under the GPL
27 	  and:
49 	  levels are 0-4 (from low to high) and by default it is set to 2.
68 	  Some systems are able to detect and correct errors in main
70 	  detection and correction (EDAC - or commonly referred to ECC
89 	  It should be noticed that keeping both GHES and a hardware-driven
102 	  Support for error detection and correction of DRAM ECC errors on
109 	  Recent Opterons (Family 10h and later) provide for Memory Error
111 	  allows the operator/user to inject Uncorrectable and Correctable
121 	  In addition, there are two control files, inject_read and inject_write,
122 	  which trigger the DRAM ECC Read and Write respectively.
128 	  Support for error detection and correction on the AMD 76x
135 	  Support for error detection and correction on the Intel
136 	  E7205, E7500, E7501 and E7505 server chipsets.
139 	tristate "Intel e752x (e7520, e7525, e7320) and 3100"
142 	  Support for error detection and correction on the Intel
150 	  Support for error detection and correction on the Intel
157 	  Support for error detection and correction on the Intel
158 	  DP82785P and E7210 server chipsets.
164 	  Support for error detection and correction on the Intel
171 	  Support for error detection and correction on the Intel
172 	  3000 and 3010 server chipsets.
178 	  Support for error detection and correction on the Intel
179 	  3200 and 3210 server chipsets.
185 	  Support for error detection and correction on the Intel
192 	  Support for error detection and correction on the Intel
199 	  Support for error detection and correction the Intel
206 	  Support for error detection and correction the Intel
209 	  and Xeon 55xx processors.
215 	  Support for error detection and correction on the Intel
222 	  Support for error detection and correction on the Radisys
229 	  Support for error detection and correction the Intel
236 	  Support for error detection and correction the Intel
243 	  Support for error detection and correction the Intel
251 	  Support for error detection and correction the Intel
252 	  Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
258 	  Support for error detection and correction on the Freescale
265 	  Support for error detection and correction on the Marvell
266 	  MV64360 and MV64460 chipsets.
273 	  Support for error detection and correction on PA Semi
280 	  Support for error detection and correction on the
291 	  440SP, 440SPe, 460EX, 460GT and 460SX.
297 	  Support for error detection and correction on the
306 	  Support for error detection and correction on the
315 	  Support for error detection and correction on the
316 	  IBM CPC925 Bridge and Memory Controller, which is
325 	  Support for error detection and correction on the
332 	  Support for error detection and correction on the
339 	  Support for error detection and correction on the
346 	  Support for error detection and correction on the primary caches of
353 	  Support for error detection and correction on the
360 	  Support for error detection and correction on the
367 	  Support for error detection and correction on the
374 	  Support for error detection and correction on the
383 	  Support for error detection and correction on the Synopsys DDR
390 	  Support for error detection and correction on the