148 	writel_relaxed(val, phy->base + REG_ZX_CTRL);  in zx_dma_terminate_chan()
151 	writel_relaxed(val, d->base + REG_ZX_TC_IRQ_RAW);  in zx_dma_terminate_chan()
152 	writel_relaxed(val, d->base + REG_ZX_SRC_ERR_IRQ_RAW);  in zx_dma_terminate_chan()
153 	writel_relaxed(val, d->base + REG_ZX_DST_ERR_IRQ_RAW);  in zx_dma_terminate_chan()
154 	writel_relaxed(val, d->base + REG_ZX_CFG_ERR_IRQ_RAW);  in zx_dma_terminate_chan()
159 	writel_relaxed(hw->saddr, phy->base + REG_ZX_SRC_ADDR);  in zx_dma_set_desc()
160 	writel_relaxed(hw->daddr, phy->base + REG_ZX_DST_ADDR);  in zx_dma_set_desc()
161 	writel_relaxed(hw->src_x, phy->base + REG_ZX_TX_X_COUNT);  in zx_dma_set_desc()
162 	writel_relaxed(0, phy->base + REG_ZX_TX_ZY_COUNT);  in zx_dma_set_desc()
163 	writel_relaxed(0, phy->base + REG_ZX_SRC_ZY_STEP);  in zx_dma_set_desc()
164 	writel_relaxed(0, phy->base + REG_ZX_DST_ZY_STEP);  in zx_dma_set_desc()
165 	writel_relaxed(hw->lli, phy->base + REG_ZX_LLI_ADDR);  in zx_dma_set_desc()
166 	writel_relaxed(hw->ctr, phy->base + REG_ZX_CTRL);  in zx_dma_set_desc()
182 	writel_relaxed(0x0, d->base + REG_ZX_DMA_ARB);  in zx_dma_init_state()
184 	writel_relaxed(0xffffffff, d->base + REG_ZX_TC_IRQ_RAW);  in zx_dma_init_state()
185 	writel_relaxed(0xffffffff, d->base + REG_ZX_SRC_ERR_IRQ_RAW);  in zx_dma_init_state()
186 	writel_relaxed(0xffffffff, d->base + REG_ZX_DST_ERR_IRQ_RAW);  in zx_dma_init_state()
187 	writel_relaxed(0xffffffff, d->base + REG_ZX_CFG_ERR_IRQ_RAW);  in zx_dma_init_state()
310 	writel_relaxed(irq_chan, d->base + REG_ZX_TC_IRQ_RAW);  in zx_dma_int_handler()
311 	writel_relaxed(serr, d->base + REG_ZX_SRC_ERR_IRQ_RAW);  in zx_dma_int_handler()
312 	writel_relaxed(derr, d->base + REG_ZX_DST_ERR_IRQ_RAW);  in zx_dma_int_handler()
313 	writel_relaxed(cfg, d->base + REG_ZX_CFG_ERR_IRQ_RAW);  in zx_dma_int_handler()
701 	writel_relaxed(val, c->phy->base + REG_ZX_CTRL);  in zx_dma_transfer_pause()
713 	writel_relaxed(val, c->phy->base + REG_ZX_CTRL);  in zx_dma_transfer_resume()