Lines Matching refs:tdc
180 typedef void (*dma_isr_handler)(struct tegra_dma_channel *tdc,
246 static inline void tdc_write(struct tegra_dma_channel *tdc, in tdc_write() argument
249 writel(val, tdc->chan_addr + reg); in tdc_write()
252 static inline u32 tdc_read(struct tegra_dma_channel *tdc, u32 reg) in tdc_read() argument
254 return readl(tdc->chan_addr + reg); in tdc_read()
268 static inline struct device *tdc2dev(struct tegra_dma_channel *tdc) in tdc2dev() argument
270 return &tdc->dma_chan.dev->device; in tdc2dev()
279 struct tegra_dma_channel *tdc) in tegra_dma_desc_get() argument
284 spin_lock_irqsave(&tdc->lock, flags); in tegra_dma_desc_get()
287 list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) { in tegra_dma_desc_get()
290 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_desc_get()
296 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_desc_get()
301 dev_err(tdc2dev(tdc), "dma_desc alloc failed\n"); in tegra_dma_desc_get()
305 dma_async_tx_descriptor_init(&dma_desc->txd, &tdc->dma_chan); in tegra_dma_desc_get()
311 static void tegra_dma_desc_put(struct tegra_dma_channel *tdc, in tegra_dma_desc_put() argument
316 spin_lock_irqsave(&tdc->lock, flags); in tegra_dma_desc_put()
318 list_splice_init(&dma_desc->tx_list, &tdc->free_sg_req); in tegra_dma_desc_put()
319 list_add_tail(&dma_desc->node, &tdc->free_dma_desc); in tegra_dma_desc_put()
320 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_desc_put()
324 struct tegra_dma_channel *tdc) in tegra_dma_sg_req_get() argument
329 spin_lock_irqsave(&tdc->lock, flags); in tegra_dma_sg_req_get()
330 if (!list_empty(&tdc->free_sg_req)) { in tegra_dma_sg_req_get()
331 sg_req = list_first_entry(&tdc->free_sg_req, in tegra_dma_sg_req_get()
334 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_sg_req_get()
337 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_sg_req_get()
341 dev_err(tdc2dev(tdc), "sg_req alloc failed\n"); in tegra_dma_sg_req_get()
348 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_slave_config() local
350 if (!list_empty(&tdc->pending_sg_req)) { in tegra_dma_slave_config()
351 dev_err(tdc2dev(tdc), "Configuration not allowed\n"); in tegra_dma_slave_config()
355 memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig)); in tegra_dma_slave_config()
356 if (!tdc->slave_id) in tegra_dma_slave_config()
357 tdc->slave_id = sconfig->slave_id; in tegra_dma_slave_config()
358 tdc->config_init = true; in tegra_dma_slave_config()
362 static void tegra_dma_global_pause(struct tegra_dma_channel *tdc, in tegra_dma_global_pause() argument
365 struct tegra_dma *tdma = tdc->tdma; in tegra_dma_global_pause()
369 if (tdc->tdma->global_pause_count == 0) { in tegra_dma_global_pause()
375 tdc->tdma->global_pause_count++; in tegra_dma_global_pause()
380 static void tegra_dma_global_resume(struct tegra_dma_channel *tdc) in tegra_dma_global_resume() argument
382 struct tegra_dma *tdma = tdc->tdma; in tegra_dma_global_resume()
386 if (WARN_ON(tdc->tdma->global_pause_count == 0)) in tegra_dma_global_resume()
389 if (--tdc->tdma->global_pause_count == 0) in tegra_dma_global_resume()
397 static void tegra_dma_pause(struct tegra_dma_channel *tdc, in tegra_dma_pause() argument
400 struct tegra_dma *tdma = tdc->tdma; in tegra_dma_pause()
403 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSRE, in tegra_dma_pause()
408 tegra_dma_global_pause(tdc, wait_for_burst_complete); in tegra_dma_pause()
412 static void tegra_dma_resume(struct tegra_dma_channel *tdc) in tegra_dma_resume() argument
414 struct tegra_dma *tdma = tdc->tdma; in tegra_dma_resume()
417 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSRE, 0); in tegra_dma_resume()
419 tegra_dma_global_resume(tdc); in tegra_dma_resume()
423 static void tegra_dma_stop(struct tegra_dma_channel *tdc) in tegra_dma_stop() argument
429 csr = tdc_read(tdc, TEGRA_APBDMA_CHAN_CSR); in tegra_dma_stop()
431 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr); in tegra_dma_stop()
435 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr); in tegra_dma_stop()
438 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS); in tegra_dma_stop()
440 dev_dbg(tdc2dev(tdc), "%s():clearing interrupt\n", __func__); in tegra_dma_stop()
441 tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status); in tegra_dma_stop()
443 tdc->busy = false; in tegra_dma_stop()
446 static void tegra_dma_start(struct tegra_dma_channel *tdc, in tegra_dma_start() argument
451 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, ch_regs->csr); in tegra_dma_start()
452 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBSEQ, ch_regs->apb_seq); in tegra_dma_start()
453 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, ch_regs->apb_ptr); in tegra_dma_start()
454 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBSEQ, ch_regs->ahb_seq); in tegra_dma_start()
455 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, ch_regs->ahb_ptr); in tegra_dma_start()
456 if (tdc->tdma->chip_data->support_separate_wcount_reg) in tegra_dma_start()
457 tdc_write(tdc, TEGRA_APBDMA_CHAN_WCOUNT, ch_regs->wcount); in tegra_dma_start()
460 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, in tegra_dma_start()
464 static void tegra_dma_configure_for_next(struct tegra_dma_channel *tdc, in tegra_dma_configure_for_next() argument
480 tegra_dma_pause(tdc, false); in tegra_dma_configure_for_next()
481 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS); in tegra_dma_configure_for_next()
488 dev_err(tdc2dev(tdc), in tegra_dma_configure_for_next()
490 tegra_dma_resume(tdc); in tegra_dma_configure_for_next()
495 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, nsg_req->ch_regs.apb_ptr); in tegra_dma_configure_for_next()
496 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, nsg_req->ch_regs.ahb_ptr); in tegra_dma_configure_for_next()
497 if (tdc->tdma->chip_data->support_separate_wcount_reg) in tegra_dma_configure_for_next()
498 tdc_write(tdc, TEGRA_APBDMA_CHAN_WCOUNT, in tegra_dma_configure_for_next()
500 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, in tegra_dma_configure_for_next()
504 tegra_dma_resume(tdc); in tegra_dma_configure_for_next()
507 static void tdc_start_head_req(struct tegra_dma_channel *tdc) in tdc_start_head_req() argument
511 if (list_empty(&tdc->pending_sg_req)) in tdc_start_head_req()
514 sg_req = list_first_entry(&tdc->pending_sg_req, in tdc_start_head_req()
516 tegra_dma_start(tdc, sg_req); in tdc_start_head_req()
518 tdc->busy = true; in tdc_start_head_req()
521 static void tdc_configure_next_head_desc(struct tegra_dma_channel *tdc) in tdc_configure_next_head_desc() argument
526 if (list_empty(&tdc->pending_sg_req)) in tdc_configure_next_head_desc()
529 hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node); in tdc_configure_next_head_desc()
530 if (!list_is_last(&hsgreq->node, &tdc->pending_sg_req)) { in tdc_configure_next_head_desc()
533 tegra_dma_configure_for_next(tdc, hnsgreq); in tdc_configure_next_head_desc()
537 static inline int get_current_xferred_count(struct tegra_dma_channel *tdc, in get_current_xferred_count() argument
543 static void tegra_dma_abort_all(struct tegra_dma_channel *tdc) in tegra_dma_abort_all() argument
548 while (!list_empty(&tdc->pending_sg_req)) { in tegra_dma_abort_all()
549 sgreq = list_first_entry(&tdc->pending_sg_req, in tegra_dma_abort_all()
551 list_move_tail(&sgreq->node, &tdc->free_sg_req); in tegra_dma_abort_all()
555 list_add_tail(&dma_desc->node, &tdc->free_dma_desc); in tegra_dma_abort_all()
560 &tdc->cb_desc); in tegra_dma_abort_all()
564 tdc->isr_handler = NULL; in tegra_dma_abort_all()
567 static bool handle_continuous_head_request(struct tegra_dma_channel *tdc, in handle_continuous_head_request() argument
572 if (list_empty(&tdc->pending_sg_req)) { in handle_continuous_head_request()
573 dev_err(tdc2dev(tdc), "Dma is running without req\n"); in handle_continuous_head_request()
574 tegra_dma_stop(tdc); in handle_continuous_head_request()
583 hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node); in handle_continuous_head_request()
585 tegra_dma_stop(tdc); in handle_continuous_head_request()
586 dev_err(tdc2dev(tdc), "Error in dma transfer, aborting dma\n"); in handle_continuous_head_request()
587 tegra_dma_abort_all(tdc); in handle_continuous_head_request()
593 tdc_configure_next_head_desc(tdc); in handle_continuous_head_request()
597 static void handle_once_dma_done(struct tegra_dma_channel *tdc, in handle_once_dma_done() argument
603 tdc->busy = false; in handle_once_dma_done()
604 sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node); in handle_once_dma_done()
613 list_add_tail(&dma_desc->cb_node, &tdc->cb_desc); in handle_once_dma_done()
615 list_add_tail(&dma_desc->node, &tdc->free_dma_desc); in handle_once_dma_done()
617 list_add_tail(&sgreq->node, &tdc->free_sg_req); in handle_once_dma_done()
620 if (to_terminate || list_empty(&tdc->pending_sg_req)) in handle_once_dma_done()
623 tdc_start_head_req(tdc); in handle_once_dma_done()
626 static void handle_cont_sngl_cycle_dma_done(struct tegra_dma_channel *tdc, in handle_cont_sngl_cycle_dma_done() argument
633 sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node); in handle_cont_sngl_cycle_dma_done()
639 list_add_tail(&dma_desc->cb_node, &tdc->cb_desc); in handle_cont_sngl_cycle_dma_done()
643 if (!list_is_last(&sgreq->node, &tdc->pending_sg_req)) { in handle_cont_sngl_cycle_dma_done()
644 list_move_tail(&sgreq->node, &tdc->pending_sg_req); in handle_cont_sngl_cycle_dma_done()
646 st = handle_continuous_head_request(tdc, sgreq, to_terminate); in handle_cont_sngl_cycle_dma_done()
654 struct tegra_dma_channel *tdc = (struct tegra_dma_channel *)data; in tegra_dma_tasklet() local
661 spin_lock_irqsave(&tdc->lock, flags); in tegra_dma_tasklet()
662 while (!list_empty(&tdc->cb_desc)) { in tegra_dma_tasklet()
663 dma_desc = list_first_entry(&tdc->cb_desc, in tegra_dma_tasklet()
670 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_tasklet()
673 spin_lock_irqsave(&tdc->lock, flags); in tegra_dma_tasklet()
675 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_tasklet()
680 struct tegra_dma_channel *tdc = dev_id; in tegra_dma_isr() local
684 spin_lock_irqsave(&tdc->lock, flags); in tegra_dma_isr()
686 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS); in tegra_dma_isr()
688 tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status); in tegra_dma_isr()
689 tdc->isr_handler(tdc, false); in tegra_dma_isr()
690 tasklet_schedule(&tdc->tasklet); in tegra_dma_isr()
691 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_isr()
695 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_isr()
696 dev_info(tdc2dev(tdc), in tegra_dma_isr()
704 struct tegra_dma_channel *tdc = to_tegra_dma_chan(txd->chan); in tegra_dma_tx_submit() local
708 spin_lock_irqsave(&tdc->lock, flags); in tegra_dma_tx_submit()
711 list_splice_tail_init(&dma_desc->tx_list, &tdc->pending_sg_req); in tegra_dma_tx_submit()
712 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_tx_submit()
718 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_issue_pending() local
721 spin_lock_irqsave(&tdc->lock, flags); in tegra_dma_issue_pending()
722 if (list_empty(&tdc->pending_sg_req)) { in tegra_dma_issue_pending()
723 dev_err(tdc2dev(tdc), "No DMA request\n"); in tegra_dma_issue_pending()
726 if (!tdc->busy) { in tegra_dma_issue_pending()
727 tdc_start_head_req(tdc); in tegra_dma_issue_pending()
730 if (tdc->cyclic) { in tegra_dma_issue_pending()
736 tdc_configure_next_head_desc(tdc); in tegra_dma_issue_pending()
740 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_issue_pending()
745 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_terminate_all() local
753 spin_lock_irqsave(&tdc->lock, flags); in tegra_dma_terminate_all()
754 if (list_empty(&tdc->pending_sg_req)) { in tegra_dma_terminate_all()
755 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_terminate_all()
759 if (!tdc->busy) in tegra_dma_terminate_all()
763 tegra_dma_pause(tdc, true); in tegra_dma_terminate_all()
765 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS); in tegra_dma_terminate_all()
767 dev_dbg(tdc2dev(tdc), "%s():handling isr\n", __func__); in tegra_dma_terminate_all()
768 tdc->isr_handler(tdc, true); in tegra_dma_terminate_all()
769 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS); in tegra_dma_terminate_all()
771 if (tdc->tdma->chip_data->support_separate_wcount_reg) in tegra_dma_terminate_all()
772 wcount = tdc_read(tdc, TEGRA_APBDMA_CHAN_WORD_TRANSFER); in tegra_dma_terminate_all()
776 was_busy = tdc->busy; in tegra_dma_terminate_all()
777 tegra_dma_stop(tdc); in tegra_dma_terminate_all()
779 if (!list_empty(&tdc->pending_sg_req) && was_busy) { in tegra_dma_terminate_all()
780 sgreq = list_first_entry(&tdc->pending_sg_req, in tegra_dma_terminate_all()
783 get_current_xferred_count(tdc, sgreq, wcount); in tegra_dma_terminate_all()
785 tegra_dma_resume(tdc); in tegra_dma_terminate_all()
788 tegra_dma_abort_all(tdc); in tegra_dma_terminate_all()
790 while (!list_empty(&tdc->cb_desc)) { in tegra_dma_terminate_all()
791 dma_desc = list_first_entry(&tdc->cb_desc, in tegra_dma_terminate_all()
796 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_terminate_all()
803 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_tx_status() local
814 spin_lock_irqsave(&tdc->lock, flags); in tegra_dma_tx_status()
817 list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) { in tegra_dma_tx_status()
824 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_tx_status()
830 list_for_each_entry(sg_req, &tdc->pending_sg_req, node) { in tegra_dma_tx_status()
838 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_tx_status()
843 dev_dbg(tdc2dev(tdc), "cookie %d does not found\n", cookie); in tegra_dma_tx_status()
844 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_tx_status()
848 static inline int get_bus_width(struct tegra_dma_channel *tdc, in get_bus_width() argument
861 dev_warn(tdc2dev(tdc), in get_bus_width()
867 static inline int get_burst_size(struct tegra_dma_channel *tdc, in get_burst_size() argument
897 static int get_transfer_param(struct tegra_dma_channel *tdc, in get_transfer_param() argument
905 *apb_addr = tdc->dma_sconfig.dst_addr; in get_transfer_param()
906 *apb_seq = get_bus_width(tdc, tdc->dma_sconfig.dst_addr_width); in get_transfer_param()
907 *burst_size = tdc->dma_sconfig.dst_maxburst; in get_transfer_param()
908 *slave_bw = tdc->dma_sconfig.dst_addr_width; in get_transfer_param()
913 *apb_addr = tdc->dma_sconfig.src_addr; in get_transfer_param()
914 *apb_seq = get_bus_width(tdc, tdc->dma_sconfig.src_addr_width); in get_transfer_param()
915 *burst_size = tdc->dma_sconfig.src_maxburst; in get_transfer_param()
916 *slave_bw = tdc->dma_sconfig.src_addr_width; in get_transfer_param()
921 dev_err(tdc2dev(tdc), "Dma direction is not supported\n"); in get_transfer_param()
927 static void tegra_dma_prep_wcount(struct tegra_dma_channel *tdc, in tegra_dma_prep_wcount() argument
932 if (tdc->tdma->chip_data->support_separate_wcount_reg) in tegra_dma_prep_wcount()
943 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_prep_slave_sg() local
953 if (!tdc->config_init) { in tegra_dma_prep_slave_sg()
954 dev_err(tdc2dev(tdc), "dma channel is not configured\n"); in tegra_dma_prep_slave_sg()
958 dev_err(tdc2dev(tdc), "Invalid segment length %d\n", sg_len); in tegra_dma_prep_slave_sg()
962 if (get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr, in tegra_dma_prep_slave_sg()
974 csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT; in tegra_dma_prep_slave_sg()
980 dma_desc = tegra_dma_desc_get(tdc); in tegra_dma_prep_slave_sg()
982 dev_err(tdc2dev(tdc), "Dma descriptors not available\n"); in tegra_dma_prep_slave_sg()
1000 (len > tdc->tdma->chip_data->max_dma_count)) { in tegra_dma_prep_slave_sg()
1001 dev_err(tdc2dev(tdc), in tegra_dma_prep_slave_sg()
1003 tegra_dma_desc_put(tdc, dma_desc); in tegra_dma_prep_slave_sg()
1007 sg_req = tegra_dma_sg_req_get(tdc); in tegra_dma_prep_slave_sg()
1009 dev_err(tdc2dev(tdc), "Dma sg-req not available\n"); in tegra_dma_prep_slave_sg()
1010 tegra_dma_desc_put(tdc, dma_desc); in tegra_dma_prep_slave_sg()
1014 ahb_seq |= get_burst_size(tdc, burst_size, slave_bw, len); in tegra_dma_prep_slave_sg()
1020 tegra_dma_prep_wcount(tdc, &sg_req->ch_regs, len); in tegra_dma_prep_slave_sg()
1038 if (!tdc->isr_handler) { in tegra_dma_prep_slave_sg()
1039 tdc->isr_handler = handle_once_dma_done; in tegra_dma_prep_slave_sg()
1040 tdc->cyclic = false; in tegra_dma_prep_slave_sg()
1042 if (tdc->cyclic) { in tegra_dma_prep_slave_sg()
1043 dev_err(tdc2dev(tdc), "DMA configured in cyclic mode\n"); in tegra_dma_prep_slave_sg()
1044 tegra_dma_desc_put(tdc, dma_desc); in tegra_dma_prep_slave_sg()
1057 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_prep_dma_cyclic() local
1068 dev_err(tdc2dev(tdc), "Invalid buffer/period len\n"); in tegra_dma_prep_dma_cyclic()
1072 if (!tdc->config_init) { in tegra_dma_prep_dma_cyclic()
1073 dev_err(tdc2dev(tdc), "DMA slave is not configured\n"); in tegra_dma_prep_dma_cyclic()
1083 if (tdc->busy) { in tegra_dma_prep_dma_cyclic()
1084 dev_err(tdc2dev(tdc), "Request not allowed when dma running\n"); in tegra_dma_prep_dma_cyclic()
1093 dev_err(tdc2dev(tdc), "buf_len is not multiple of period_len\n"); in tegra_dma_prep_dma_cyclic()
1099 (len > tdc->tdma->chip_data->max_dma_count)) { in tegra_dma_prep_dma_cyclic()
1100 dev_err(tdc2dev(tdc), "Req len/mem address is not correct\n"); in tegra_dma_prep_dma_cyclic()
1104 if (get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr, in tegra_dma_prep_dma_cyclic()
1116 csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT; in tegra_dma_prep_dma_cyclic()
1120 dma_desc = tegra_dma_desc_get(tdc); in tegra_dma_prep_dma_cyclic()
1122 dev_err(tdc2dev(tdc), "not enough descriptors available\n"); in tegra_dma_prep_dma_cyclic()
1136 sg_req = tegra_dma_sg_req_get(tdc); in tegra_dma_prep_dma_cyclic()
1138 dev_err(tdc2dev(tdc), "Dma sg-req not available\n"); in tegra_dma_prep_dma_cyclic()
1139 tegra_dma_desc_put(tdc, dma_desc); in tegra_dma_prep_dma_cyclic()
1143 ahb_seq |= get_burst_size(tdc, burst_size, slave_bw, len); in tegra_dma_prep_dma_cyclic()
1147 tegra_dma_prep_wcount(tdc, &sg_req->ch_regs, len); in tegra_dma_prep_dma_cyclic()
1167 if (!tdc->isr_handler) { in tegra_dma_prep_dma_cyclic()
1168 tdc->isr_handler = handle_cont_sngl_cycle_dma_done; in tegra_dma_prep_dma_cyclic()
1169 tdc->cyclic = true; in tegra_dma_prep_dma_cyclic()
1171 if (!tdc->cyclic) { in tegra_dma_prep_dma_cyclic()
1172 dev_err(tdc2dev(tdc), "DMA configuration conflict\n"); in tegra_dma_prep_dma_cyclic()
1173 tegra_dma_desc_put(tdc, dma_desc); in tegra_dma_prep_dma_cyclic()
1183 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_alloc_chan_resources() local
1184 struct tegra_dma *tdma = tdc->tdma; in tegra_dma_alloc_chan_resources()
1187 dma_cookie_init(&tdc->dma_chan); in tegra_dma_alloc_chan_resources()
1188 tdc->config_init = false; in tegra_dma_alloc_chan_resources()
1191 dev_err(tdc2dev(tdc), "clk_prepare_enable failed: %d\n", ret); in tegra_dma_alloc_chan_resources()
1197 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_free_chan_resources() local
1198 struct tegra_dma *tdma = tdc->tdma; in tegra_dma_free_chan_resources()
1209 dev_dbg(tdc2dev(tdc), "Freeing channel %d\n", tdc->id); in tegra_dma_free_chan_resources()
1211 if (tdc->busy) in tegra_dma_free_chan_resources()
1214 spin_lock_irqsave(&tdc->lock, flags); in tegra_dma_free_chan_resources()
1215 list_splice_init(&tdc->pending_sg_req, &sg_req_list); in tegra_dma_free_chan_resources()
1216 list_splice_init(&tdc->free_sg_req, &sg_req_list); in tegra_dma_free_chan_resources()
1217 list_splice_init(&tdc->free_dma_desc, &dma_desc_list); in tegra_dma_free_chan_resources()
1218 INIT_LIST_HEAD(&tdc->cb_desc); in tegra_dma_free_chan_resources()
1219 tdc->config_init = false; in tegra_dma_free_chan_resources()
1220 tdc->isr_handler = NULL; in tegra_dma_free_chan_resources()
1221 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_free_chan_resources()
1237 tdc->slave_id = 0; in tegra_dma_free_chan_resources()
1245 struct tegra_dma_channel *tdc; in tegra_dma_of_xlate() local
1251 tdc = to_tegra_dma_chan(chan); in tegra_dma_of_xlate()
1252 tdc->slave_id = dma_spec->args[0]; in tegra_dma_of_xlate()
1389 struct tegra_dma_channel *tdc = &tdma->channels[i]; in tegra_dma_probe() local
1391 tdc->chan_addr = tdma->base_addr + in tegra_dma_probe()
1401 tdc->irq = res->start; in tegra_dma_probe()
1402 snprintf(tdc->name, sizeof(tdc->name), "apbdma.%d", i); in tegra_dma_probe()
1403 ret = devm_request_irq(&pdev->dev, tdc->irq, in tegra_dma_probe()
1404 tegra_dma_isr, 0, tdc->name, tdc); in tegra_dma_probe()
1412 tdc->dma_chan.device = &tdma->dma_dev; in tegra_dma_probe()
1413 dma_cookie_init(&tdc->dma_chan); in tegra_dma_probe()
1414 list_add_tail(&tdc->dma_chan.device_node, in tegra_dma_probe()
1416 tdc->tdma = tdma; in tegra_dma_probe()
1417 tdc->id = i; in tegra_dma_probe()
1419 tasklet_init(&tdc->tasklet, tegra_dma_tasklet, in tegra_dma_probe()
1420 (unsigned long)tdc); in tegra_dma_probe()
1421 spin_lock_init(&tdc->lock); in tegra_dma_probe()
1423 INIT_LIST_HEAD(&tdc->pending_sg_req); in tegra_dma_probe()
1424 INIT_LIST_HEAD(&tdc->free_sg_req); in tegra_dma_probe()
1425 INIT_LIST_HEAD(&tdc->free_dma_desc); in tegra_dma_probe()
1426 INIT_LIST_HEAD(&tdc->cb_desc); in tegra_dma_probe()
1484 struct tegra_dma_channel *tdc = &tdma->channels[i]; in tegra_dma_probe() local
1485 tasklet_kill(&tdc->tasklet); in tegra_dma_probe()
1499 struct tegra_dma_channel *tdc; in tegra_dma_remove() local
1504 tdc = &tdma->channels[i]; in tegra_dma_remove()
1505 tasklet_kill(&tdc->tasklet); in tegra_dma_remove()
1552 struct tegra_dma_channel *tdc = &tdma->channels[i]; in tegra_dma_pm_suspend() local
1553 struct tegra_dma_channel_regs *ch_reg = &tdc->channel_reg; in tegra_dma_pm_suspend()
1555 ch_reg->csr = tdc_read(tdc, TEGRA_APBDMA_CHAN_CSR); in tegra_dma_pm_suspend()
1556 ch_reg->ahb_ptr = tdc_read(tdc, TEGRA_APBDMA_CHAN_AHBPTR); in tegra_dma_pm_suspend()
1557 ch_reg->apb_ptr = tdc_read(tdc, TEGRA_APBDMA_CHAN_APBPTR); in tegra_dma_pm_suspend()
1558 ch_reg->ahb_seq = tdc_read(tdc, TEGRA_APBDMA_CHAN_AHBSEQ); in tegra_dma_pm_suspend()
1559 ch_reg->apb_seq = tdc_read(tdc, TEGRA_APBDMA_CHAN_APBSEQ); in tegra_dma_pm_suspend()
1583 struct tegra_dma_channel *tdc = &tdma->channels[i]; in tegra_dma_pm_resume() local
1584 struct tegra_dma_channel_regs *ch_reg = &tdc->channel_reg; in tegra_dma_pm_resume()
1586 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBSEQ, ch_reg->apb_seq); in tegra_dma_pm_resume()
1587 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, ch_reg->apb_ptr); in tegra_dma_pm_resume()
1588 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBSEQ, ch_reg->ahb_seq); in tegra_dma_pm_resume()
1589 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, ch_reg->ahb_ptr); in tegra_dma_pm_resume()
1590 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, in tegra_dma_pm_resume()