566 	void __iomem			 *virtbase;  member
616 	return chan->base->virtbase + D40_DREG_PCBASE +  in chan_base()
1076 		active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;  in __d40_execute_command_phy()
1078 		active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;  in __d40_execute_command_phy()
1293 		active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;  in __d40_execute_command_log()
1295 		active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;  in __d40_execute_command_log()
1377 	writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base);  in d40_config_write()
1382 	writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base);  in d40_config_write()
1678 		regs[i] = readl(base->virtbase + il[i].src);  in d40_handle_interrupt()
1706 		writel(BIT(idx), base->virtbase + il[row].clr);  in d40_handle_interrupt()
2088 			active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;  in d40_is_paused()
2090 			active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;  in d40_is_paused()
2346 	writel(bit, d40c->base->virtbase + prioreg + group * 4);  in __d40_set_prio_rt()
2347 	writel(bit, d40c->base->virtbase + rtreg + group * 4);  in __d40_set_prio_rt()
3001 		addr = base->virtbase + D40_DREG_PCBASE + i * D40_DREG_PCDELTA;  in d40_save_restore_registers()
3011 	dma40_backup(base->virtbase, base->reg_val_backup,  in d40_save_restore_registers()
3017 		dma40_backup(base->virtbase, base->reg_val_backup_v4,  in d40_save_restore_registers()
3033 			       base->virtbase + D40_DREG_GCC);  in dma40_runtime_suspend()
3046 		       base->virtbase + D40_DREG_GCC);  in dma40_runtime_resume()
3068 	val[0] = readl(base->virtbase + D40_DREG_PRSME);  in d40_phy_res_init()
3069 	val[1] = readl(base->virtbase + D40_DREG_PRSMO);  in d40_phy_res_init()
3119 	val[0] = readl(base->virtbase + D40_DREG_PRTYP);  in d40_phy_res_init()
3138 	writel(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC);  in d40_phy_res_init()
3148 	void __iomem *virtbase = NULL;  in d40_hw_detect_init()  local
3181 	virtbase = ioremap(res->start, resource_size(res));  in d40_hw_detect_init()
3182 	if (!virtbase)  in d40_hw_detect_init()
3187 		pid |= (readl(virtbase + resource_size(res) - 0x20 + 4 * i)  in d40_hw_detect_init()
3190 		cid |= (readl(virtbase + resource_size(res) - 0x10 + 4 * i)  in d40_hw_detect_init()
3222 		num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;  in d40_hw_detect_init()
3252 	base->virtbase = virtbase;  in d40_hw_detect_init()
3330 	if (virtbase)  in d40_hw_detect_init()
3331 		iounmap(virtbase);  in d40_hw_detect_init()
3335 	if (virtbase)  in d40_hw_detect_init()
3336 		iounmap(virtbase);  in d40_hw_detect_init()
3363 		       base->virtbase + dma_init_reg[i].reg);  in d40_hw_init()
3388 	writel(prmseo[1], base->virtbase + D40_DREG_PRMSE);  in d40_hw_init()
3389 	writel(prmseo[0], base->virtbase + D40_DREG_PRMSO);  in d40_hw_init()
3390 	writel(activeo[1], base->virtbase + D40_DREG_ACTIVE);  in d40_hw_init()
3391 	writel(activeo[0], base->virtbase + D40_DREG_ACTIVO);  in d40_hw_init()
3394 	writel(pcmis, base->virtbase + base->gen_dmac.interrupt_en);  in d40_hw_init()
3397 	writel(pcicr, base->virtbase + base->gen_dmac.interrupt_clear);  in d40_hw_init()
3482 	       base->virtbase + D40_DREG_LCLA);  in d40_lcla_allocate()
3592 	val = readl(base->virtbase + D40_DREG_LCPA);  in d40_probe()
3598 		writel(res->start, base->virtbase + D40_DREG_LCPA);  in d40_probe()
3623 		writel(res->start, base->virtbase + D40_DREG_LCLA);  in d40_probe()
3663 	writel_relaxed(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC);  in d40_probe()
3699 		if (base->virtbase)  in d40_probe()
3700 			iounmap(base->virtbase);  in d40_probe()