596 	struct d40_gen_dmac		  gen_dmac;  member
1670 	u32 regs[base->gen_dmac.il_size];  in d40_handle_interrupt()
1671 	struct d40_interrupt_lookup *il = base->gen_dmac.il;  in d40_handle_interrupt()
1672 	u32 il_size = base->gen_dmac.il_size;  in d40_handle_interrupt()
2326 	struct d40_gen_dmac *dmac = &d40c->base->gen_dmac;  in __d40_set_prio_rt()
3016 	if (base->gen_dmac.backup)  in d40_save_restore_registers()
3018 			     base->gen_dmac.backup,  in d40_save_restore_registers()
3019 			base->gen_dmac.backup_size,  in d40_save_restore_registers()
3259 		base->gen_dmac.backup = d40_backup_regs_v4b;  in d40_hw_detect_init()
3260 		base->gen_dmac.backup_size = BACKUP_REGS_SZ_V4B;  in d40_hw_detect_init()
3261 		base->gen_dmac.interrupt_en = D40_DREG_CPCMIS;  in d40_hw_detect_init()
3262 		base->gen_dmac.interrupt_clear = D40_DREG_CPCICR;  in d40_hw_detect_init()
3263 		base->gen_dmac.realtime_en = D40_DREG_CRSEG1;  in d40_hw_detect_init()
3264 		base->gen_dmac.realtime_clear = D40_DREG_CRCEG1;  in d40_hw_detect_init()
3265 		base->gen_dmac.high_prio_en = D40_DREG_CPSEG1;  in d40_hw_detect_init()
3266 		base->gen_dmac.high_prio_clear = D40_DREG_CPCEG1;  in d40_hw_detect_init()
3267 		base->gen_dmac.il = il_v4b;  in d40_hw_detect_init()
3268 		base->gen_dmac.il_size = ARRAY_SIZE(il_v4b);  in d40_hw_detect_init()
3269 		base->gen_dmac.init_reg = dma_init_reg_v4b;  in d40_hw_detect_init()
3270 		base->gen_dmac.init_reg_size = ARRAY_SIZE(dma_init_reg_v4b);  in d40_hw_detect_init()
3273 			base->gen_dmac.backup = d40_backup_regs_v4a;  in d40_hw_detect_init()
3274 			base->gen_dmac.backup_size = BACKUP_REGS_SZ_V4A;  in d40_hw_detect_init()
3276 		base->gen_dmac.interrupt_en = D40_DREG_PCMIS;  in d40_hw_detect_init()
3277 		base->gen_dmac.interrupt_clear = D40_DREG_PCICR;  in d40_hw_detect_init()
3278 		base->gen_dmac.realtime_en = D40_DREG_RSEG1;  in d40_hw_detect_init()
3279 		base->gen_dmac.realtime_clear = D40_DREG_RCEG1;  in d40_hw_detect_init()
3280 		base->gen_dmac.high_prio_en = D40_DREG_PSEG1;  in d40_hw_detect_init()
3281 		base->gen_dmac.high_prio_clear = D40_DREG_PCEG1;  in d40_hw_detect_init()
3282 		base->gen_dmac.il = il_v4a;  in d40_hw_detect_init()
3283 		base->gen_dmac.il_size = ARRAY_SIZE(il_v4a);  in d40_hw_detect_init()
3284 		base->gen_dmac.init_reg = dma_init_reg_v4a;  in d40_hw_detect_init()
3285 		base->gen_dmac.init_reg_size = ARRAY_SIZE(dma_init_reg_v4a);  in d40_hw_detect_init()
3358 	struct d40_reg_val *dma_init_reg = base->gen_dmac.init_reg;  in d40_hw_init()
3359 	u32 reg_size = base->gen_dmac.init_reg_size;  in d40_hw_init()
3394 	writel(pcmis, base->virtbase + base->gen_dmac.interrupt_en);  in d40_hw_init()
3397 	writel(pcicr, base->virtbase + base->gen_dmac.interrupt_clear);  in d40_hw_init()
3400 	base->gen_dmac.init_reg = NULL;  in d40_hw_init()
3401 	base->gen_dmac.init_reg_size = 0;  in d40_hw_init()