168 		writel_relaxed((sdesc->dir << SIRFSOC_DMA_DIR_CTRL_BIT_ATLAS7) |  in sirfsoc_dma_execute_hw_a7v2()
175 		writel_relaxed(sdesc->xlen, base + SIRFSOC_DMA_CH_XLEN);  in sirfsoc_dma_execute_hw_a7v2()
176 		writel_relaxed(sdesc->ylen, base + SIRFSOC_DMA_CH_YLEN);  in sirfsoc_dma_execute_hw_a7v2()
177 		writel_relaxed(sdesc->width, base + SIRFSOC_DMA_WIDTH_ATLAS7);  in sirfsoc_dma_execute_hw_a7v2()
178 		writel_relaxed((sdesc->width*((sdesc->ylen+1)>>1)),  in sirfsoc_dma_execute_hw_a7v2()
180 		writel_relaxed((sdesc->dir << SIRFSOC_DMA_DIR_CTRL_BIT_ATLAS7) |  in sirfsoc_dma_execute_hw_a7v2()
185 	writel_relaxed(sdesc->chain ? SIRFSOC_DMA_INT_END_INT_ATLAS7 :  in sirfsoc_dma_execute_hw_a7v2()
197 	writel_relaxed(1, base + SIRFSOC_DMA_IOBG_SCMD_EN);  in sirfsoc_dma_execute_hw_a7v1()
198 	writel_relaxed((1 << cid), base + SIRFSOC_DMA_EARLY_RESP_SET);  in sirfsoc_dma_execute_hw_a7v1()
199 	writel_relaxed(sdesc->width, base + SIRFSOC_DMA_WIDTH_0 + cid * 4);  in sirfsoc_dma_execute_hw_a7v1()
200 	writel_relaxed(cid | (burst_mode << SIRFSOC_DMA_MODE_CTRL_BIT) |  in sirfsoc_dma_execute_hw_a7v1()
203 	writel_relaxed(sdesc->xlen, base + cid * 0x10 + SIRFSOC_DMA_CH_XLEN);  in sirfsoc_dma_execute_hw_a7v1()
204 	writel_relaxed(sdesc->ylen, base + cid * 0x10 + SIRFSOC_DMA_CH_YLEN);  in sirfsoc_dma_execute_hw_a7v1()
205 	writel_relaxed(readl_relaxed(base + SIRFSOC_DMA_INT_EN) |  in sirfsoc_dma_execute_hw_a7v1()
219 	writel_relaxed(sdesc->width, base + SIRFSOC_DMA_WIDTH_0 + cid * 4);  in sirfsoc_dma_execute_hw_a6()
220 	writel_relaxed(cid | (burst_mode << SIRFSOC_DMA_MODE_CTRL_BIT) |  in sirfsoc_dma_execute_hw_a6()
223 	writel_relaxed(sdesc->xlen, base + cid * 0x10 + SIRFSOC_DMA_CH_XLEN);  in sirfsoc_dma_execute_hw_a6()
224 	writel_relaxed(sdesc->ylen, base + cid * 0x10 + SIRFSOC_DMA_CH_YLEN);  in sirfsoc_dma_execute_hw_a6()
225 	writel_relaxed(readl_relaxed(base + SIRFSOC_DMA_INT_EN) |  in sirfsoc_dma_execute_hw_a6()
282 			writel_relaxed(1 << ch, reg);  in sirfsoc_dma_irq()
304 		writel_relaxed(SIRFSOC_DMA_INT_ALL_ATLAS7, reg);  in sirfsoc_dma_irq()
457 		writel_relaxed(1 << cid, sdma->base + SIRFSOC_DMA_INT_EN_CLR);  in sirfsoc_dma_terminate_all()
458 		writel_relaxed(1 << cid, sdma->base + SIRFSOC_DMA_CH_INT);  in sirfsoc_dma_terminate_all()
459 		writel_relaxed((1 << cid) | 1 << (cid + 16),  in sirfsoc_dma_terminate_all()
462 		writel_relaxed(1 << cid, sdma->base + SIRFSOC_DMA_CH_VALID);  in sirfsoc_dma_terminate_all()
465 		writel_relaxed(0, sdma->base + SIRFSOC_DMA_INT_EN_ATLAS7);  in sirfsoc_dma_terminate_all()
466 		writel_relaxed(SIRFSOC_DMA_INT_ALL_ATLAS7,  in sirfsoc_dma_terminate_all()
468 		writel_relaxed(0, sdma->base + SIRFSOC_DMA_LOOP_CTRL_ATLAS7);  in sirfsoc_dma_terminate_all()
469 		writel_relaxed(0, sdma->base + SIRFSOC_DMA_VALID_ATLAS7);  in sirfsoc_dma_terminate_all()
472 		writel_relaxed(readl_relaxed(sdma->base + SIRFSOC_DMA_INT_EN) &  in sirfsoc_dma_terminate_all()
474 		writel_relaxed(readl_relaxed(sdma->base +  in sirfsoc_dma_terminate_all()
478 		writel_relaxed(1 << cid, sdma->base + SIRFSOC_DMA_CH_VALID);  in sirfsoc_dma_terminate_all()
503 		writel_relaxed((1 << cid) | 1 << (cid + 16),  in sirfsoc_dma_pause_chan()
508 		writel_relaxed(0, sdma->base + SIRFSOC_DMA_LOOP_CTRL_ATLAS7);  in sirfsoc_dma_pause_chan()
511 		writel_relaxed(readl_relaxed(sdma->base +  in sirfsoc_dma_pause_chan()
536 		writel_relaxed((1 << cid) | 1 << (cid + 16),  in sirfsoc_dma_resume_chan()
540 		writel_relaxed(0x10001,  in sirfsoc_dma_resume_chan()
544 		writel_relaxed(readl_relaxed(sdma->base +  in sirfsoc_dma_resume_chan()
1092 	writel_relaxed(save->interrupt_en, sdma->base + int_offset);  in sirfsoc_dma_pm_resume()
1100 		writel_relaxed(sdesc->width,  in sirfsoc_dma_pm_resume()
1102 		writel_relaxed(sdesc->xlen,  in sirfsoc_dma_pm_resume()
1104 		writel_relaxed(sdesc->ylen,  in sirfsoc_dma_pm_resume()
1106 		writel_relaxed(save->ctrl[ch],  in sirfsoc_dma_pm_resume()
1109 			writel_relaxed(sdesc->addr,  in sirfsoc_dma_pm_resume()
1112 			writel_relaxed(sdesc->addr >> 2,  in sirfsoc_dma_pm_resume()