1535 	dev_dbg(chan->device->common.dev, "\tfree slot %llx: %d stride: %d\n",  in ppc440spe_adma_clean_slot()
1558 	dev_dbg(chan->device->common.dev, "ppc440spe adma%d: %s\n",  in __ppc440spe_adma_slot_cleanup()
1573 		dev_dbg(chan->device->common.dev, "\tcookie: %d slot: %d "  in __ppc440spe_adma_slot_cleanup()
1639 						chan->common.completed_cookie = cookie;  in __ppc440spe_adma_slot_cleanup()
1669 		chan->common.completed_cookie = cookie;  in __ppc440spe_adma_slot_cleanup()
1832 	dev_dbg(ppc440spe_chan->device->common.dev,  in ppc440spe_adma_alloc_chan_resources()
1898 	dev_dbg(chan->device->common.dev, "ppc440spe adma%d: pending: %d\n",  in ppc440spe_adma_check_threshold()
1950 	dev_dbg(chan->device->common.dev,  in ppc440spe_adma_tx_submit()
1970 	dev_dbg(ppc440spe_chan->device->common.dev,  in ppc440spe_adma_prep_dma_interrupt()
2009 	dev_dbg(ppc440spe_chan->device->common.dev,  in ppc440spe_adma_prep_dma_memcpy()
2050 	dev_dbg(ppc440spe_chan->device->common.dev,  in ppc440spe_adma_prep_dma_xor()
2573 	dev_dbg(ppc440spe_chan->device->common.dev,  in ppc440spe_adma_prep_dma_pq()
3573 	dev_dbg(ppc440spe_chan->device->common.dev,  in ppc440spe_adma_free_chan_resources()
3614 	dev_dbg(chan->device->common.dev,  in ppc440spe_adma_eot_handler()
3631 	dev_dbg(chan->device->common.dev,  in ppc440spe_adma_err_handler()
3656 	dev_dbg(ppc440spe_chan->device->common.dev,  in ppc440spe_adma_issue_pending()
3677 	dev_dbg(chan->device->common.dev,  in ppc440spe_chan_start_null_xor()
3694 		chan->common.completed_cookie = cookie - 1;  in ppc440spe_chan_start_null_xor()
3767 	ppc440spe_adma_issue_pending(&chan->common);  in ppc440spe_test_raid6()
3790 		dma_cap_set(DMA_MEMCPY, adev->common.cap_mask);  in ppc440spe_adma_init_capabilities()
3791 		dma_cap_set(DMA_INTERRUPT, adev->common.cap_mask);  in ppc440spe_adma_init_capabilities()
3792 		dma_cap_set(DMA_PQ, adev->common.cap_mask);  in ppc440spe_adma_init_capabilities()
3793 		dma_cap_set(DMA_PQ_VAL, adev->common.cap_mask);  in ppc440spe_adma_init_capabilities()
3794 		dma_cap_set(DMA_XOR_VAL, adev->common.cap_mask);  in ppc440spe_adma_init_capabilities()
3797 		dma_cap_set(DMA_XOR, adev->common.cap_mask);  in ppc440spe_adma_init_capabilities()
3798 		dma_cap_set(DMA_PQ, adev->common.cap_mask);  in ppc440spe_adma_init_capabilities()
3799 		dma_cap_set(DMA_INTERRUPT, adev->common.cap_mask);  in ppc440spe_adma_init_capabilities()
3800 		adev->common.cap_mask = adev->common.cap_mask;  in ppc440spe_adma_init_capabilities()
3805 	adev->common.device_alloc_chan_resources =  in ppc440spe_adma_init_capabilities()
3807 	adev->common.device_free_chan_resources =  in ppc440spe_adma_init_capabilities()
3809 	adev->common.device_tx_status = ppc440spe_adma_tx_status;  in ppc440spe_adma_init_capabilities()
3810 	adev->common.device_issue_pending = ppc440spe_adma_issue_pending;  in ppc440spe_adma_init_capabilities()
3813 	if (dma_has_cap(DMA_MEMCPY, adev->common.cap_mask)) {  in ppc440spe_adma_init_capabilities()
3814 		adev->common.device_prep_dma_memcpy =  in ppc440spe_adma_init_capabilities()
3817 	if (dma_has_cap(DMA_XOR, adev->common.cap_mask)) {  in ppc440spe_adma_init_capabilities()
3818 		adev->common.max_xor = XOR_MAX_OPS;  in ppc440spe_adma_init_capabilities()
3819 		adev->common.device_prep_dma_xor =  in ppc440spe_adma_init_capabilities()
3822 	if (dma_has_cap(DMA_PQ, adev->common.cap_mask)) {  in ppc440spe_adma_init_capabilities()
3825 			dma_set_maxpq(&adev->common,  in ppc440spe_adma_init_capabilities()
3829 			dma_set_maxpq(&adev->common,  in ppc440spe_adma_init_capabilities()
3833 			adev->common.max_pq = XOR_MAX_OPS * 3;  in ppc440spe_adma_init_capabilities()
3836 		adev->common.device_prep_dma_pq =  in ppc440spe_adma_init_capabilities()
3839 	if (dma_has_cap(DMA_PQ_VAL, adev->common.cap_mask)) {  in ppc440spe_adma_init_capabilities()
3842 			adev->common.max_pq = DMA0_FIFO_SIZE /  in ppc440spe_adma_init_capabilities()
3846 			adev->common.max_pq = DMA1_FIFO_SIZE /  in ppc440spe_adma_init_capabilities()
3850 		adev->common.device_prep_dma_pq_val =  in ppc440spe_adma_init_capabilities()
3853 	if (dma_has_cap(DMA_XOR_VAL, adev->common.cap_mask)) {  in ppc440spe_adma_init_capabilities()
3856 			adev->common.max_xor = DMA0_FIFO_SIZE /  in ppc440spe_adma_init_capabilities()
3860 			adev->common.max_xor = DMA1_FIFO_SIZE /  in ppc440spe_adma_init_capabilities()
3864 		adev->common.device_prep_dma_xor_val =  in ppc440spe_adma_init_capabilities()
3867 	if (dma_has_cap(DMA_INTERRUPT, adev->common.cap_mask)) {  in ppc440spe_adma_init_capabilities()
3868 		adev->common.device_prep_dma_interrupt =  in ppc440spe_adma_init_capabilities()
3874 	  dma_has_cap(DMA_PQ, adev->common.cap_mask) ? "pq " : "",  in ppc440spe_adma_init_capabilities()
3875 	  dma_has_cap(DMA_PQ_VAL, adev->common.cap_mask) ? "pq_val " : "",  in ppc440spe_adma_init_capabilities()
3876 	  dma_has_cap(DMA_XOR, adev->common.cap_mask) ? "xor " : "",  in ppc440spe_adma_init_capabilities()
3877 	  dma_has_cap(DMA_XOR_VAL, adev->common.cap_mask) ? "xor_val " : "",  in ppc440spe_adma_init_capabilities()
3878 	  dma_has_cap(DMA_MEMCPY, adev->common.cap_mask) ? "memcpy " : "",  in ppc440spe_adma_init_capabilities()
3879 	  dma_has_cap(DMA_INTERRUPT, adev->common.cap_mask) ? "intr " : "");  in ppc440spe_adma_init_capabilities()
4141 	adev->common.dev = &ofdev->dev;  in ppc440spe_adma_probe()
4142 	INIT_LIST_HEAD(&adev->common.channels);  in ppc440spe_adma_probe()
4158 	chan->common.device = &adev->common;  in ppc440spe_adma_probe()
4159 	dma_cookie_init(&chan->common);  in ppc440spe_adma_probe()
4160 	list_add_tail(&chan->common.device_node, &adev->common.channels);  in ppc440spe_adma_probe()
4187 		ref->chan = &chan->common;  in ppc440spe_adma_probe()
4202 	ret = dma_async_device_register(&adev->common);  in ppc440spe_adma_probe()
4266 	dma_async_device_unregister(&adev->common);  in ppc440spe_adma_remove()
4268 	list_for_each_entry_safe(chan, _chan, &adev->common.channels,  in ppc440spe_adma_remove()