121 		writel_relaxed(val, phy->base + CX_CFG);  in k3_dma_pause_dma()
125 		writel_relaxed(val, phy->base + CX_CFG);  in k3_dma_pause_dma()
136 	writel_relaxed(val, d->base + INT_TC1_RAW);  in k3_dma_terminate_chan()
137 	writel_relaxed(val, d->base + INT_ERR1_RAW);  in k3_dma_terminate_chan()
138 	writel_relaxed(val, d->base + INT_ERR2_RAW);  in k3_dma_terminate_chan()
143 	writel_relaxed(hw->lli, phy->base + CX_LLI);  in k3_dma_set_desc()
144 	writel_relaxed(hw->count, phy->base + CX_CNT);  in k3_dma_set_desc()
145 	writel_relaxed(hw->saddr, phy->base + CX_SRC);  in k3_dma_set_desc()
146 	writel_relaxed(hw->daddr, phy->base + CX_DST);  in k3_dma_set_desc()
147 	writel_relaxed(AXI_CFG_DEFAULT, phy->base + AXI_CFG);  in k3_dma_set_desc()
148 	writel_relaxed(hw->config, phy->base + CX_CFG);  in k3_dma_set_desc()
174 		writel_relaxed(0x0, d->base + CH_PRI);  in k3_dma_enable_dma()
177 		writel_relaxed(0xffff, d->base + INT_TC1_MASK);  in k3_dma_enable_dma()
178 		writel_relaxed(0xffff, d->base + INT_ERR1_MASK);  in k3_dma_enable_dma()
179 		writel_relaxed(0xffff, d->base + INT_ERR2_MASK);  in k3_dma_enable_dma()
182 		writel_relaxed(0x0, d->base + INT_TC1_MASK);  in k3_dma_enable_dma()
183 		writel_relaxed(0x0, d->base + INT_ERR1_MASK);  in k3_dma_enable_dma()
184 		writel_relaxed(0x0, d->base + INT_ERR2_MASK);  in k3_dma_enable_dma()
219 	writel_relaxed(irq_chan, d->base + INT_TC1_RAW);  in k3_dma_int_handler()
220 	writel_relaxed(err1, d->base + INT_ERR1_RAW);  in k3_dma_int_handler()
221 	writel_relaxed(err2, d->base + INT_ERR2_RAW);  in k3_dma_int_handler()