483 	writeb(intrctrl, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET);  in ioat_dma_setup_interrupts()
488 	writeb(0, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET);  in ioat_dma_setup_interrupts()
497 	writeb(0, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET);  in ioat_disable_interrupts()
598 	dma->chancnt = readb(ioat_dma->reg_base + IOAT_CHANCNT_OFFSET);  in ioat_enumerate_channels()
605 	xfercap_log = readb(ioat_dma->reg_base + IOAT_XFERCAP_OFFSET);  in ioat_enumerate_channels()
699 	writew(IOAT_CHANCTRL_RUN, ioat_chan->reg_base + IOAT_CHANCTRL_OFFSET);  in ioat_alloc_chan_resources()
711 	       ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_LOW);  in ioat_alloc_chan_resources()
713 	       ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH);  in ioat_alloc_chan_resources()
742 	chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET);  in ioat_alloc_chan_resources()
760 	ioat_chan->reg_base = ioat_dma->reg_base + (0x80 * (idx + 1));  in ioat_init_channel()
1069 			errmask = readl(ioat_chan->reg_base +  in ioat_intr_quirk()
1073 			writel(errmask, ioat_chan->reg_base +  in ioat_intr_quirk()
1098 	ioat_dma->cap = readl(ioat_dma->reg_base + IOAT_DMA_CAP_OFFSET);  in ioat3_dma_probe()
1175 		       ioat_chan->reg_base + IOAT_DCACTRL_OFFSET);  in ioat3_dma_probe()
1185 		ioat_dma->dca = ioat_dca_init(pdev, ioat_dma->reg_base);  in ioat3_dma_probe()
1230 		chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET);  in ioat_resume()
1231 		writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET);  in ioat_resume()
1311 	d->reg_base = iobase;  in alloc_ioatdma()
1351 	device->version = readb(device->reg_base + IOAT_VER_OFFSET);  in ioat_pci_probe()