Lines Matching refs:DMA_CCR
75 #define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */ macro
325 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) | in imxdma_enable_hw()
326 CCR_CEN | CCR_ACRPT, DMA_CCR(channel)); in imxdma_enable_hw()
334 tmp = imx_dmav1_readl(imxdma, DMA_CCR(channel)); in imxdma_enable_hw()
336 DMA_CCR(channel)); in imxdma_enable_hw()
357 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) & in imxdma_disable_hw()
358 ~CCR_CEN, DMA_CCR(channel)); in imxdma_disable_hw()
369 imx_dmav1_writel(imxdma, 0, DMA_CCR(channel)); in imxdma_watchdog()
455 tmp = imx_dmav1_readl(imxdma, DMA_CCR(chno)); in dma_irq_handle_channel()
465 imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno)); in dma_irq_handle_channel()
468 DMA_CCR(chno)); in dma_irq_handle_channel()
472 imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno)); in dma_irq_handle_channel()
488 imx_dmav1_writel(imxdma, 0, DMA_CCR(chno)); in dma_irq_handle_channel()
566 DMA_CCR(imxdmac->channel)); in imxdma_xfer_desc()
584 DMA_CCR(imxdmac->channel)); in imxdma_xfer_desc()
595 DMA_CCR(imxdmac->channel)); in imxdma_xfer_desc()