Lines Matching refs:edma_shadow0_write_array
366 static inline void edma_shadow0_write_array(struct edma_cc *ecc, int offset, in edma_shadow0_write_array() function
439 edma_shadow0_write_array(ecc, SH_ICR, channel >> 5, in edma_setup_interrupt()
441 edma_shadow0_write_array(ecc, SH_IESR, channel >> 5, in edma_setup_interrupt()
444 edma_shadow0_write_array(ecc, SH_IECR, channel >> 5, in edma_setup_interrupt()
588 edma_shadow0_write_array(ecc, SH_ESR, j, mask); in edma_start()
597 edma_shadow0_write_array(ecc, SH_SECR, j, mask); in edma_start()
598 edma_shadow0_write_array(ecc, SH_EESR, j, mask); in edma_start()
611 edma_shadow0_write_array(ecc, SH_EECR, j, mask); in edma_stop()
612 edma_shadow0_write_array(ecc, SH_ECR, j, mask); in edma_stop()
613 edma_shadow0_write_array(ecc, SH_SECR, j, mask); in edma_stop()
617 edma_shadow0_write_array(ecc, SH_ICR, j, mask); in edma_stop()
636 edma_shadow0_write_array(echan->ecc, SH_EECR, channel >> 5, mask); in edma_pause()
645 edma_shadow0_write_array(echan->ecc, SH_EESR, channel >> 5, mask); in edma_resume()
654 edma_shadow0_write_array(ecc, SH_ESR, (channel >> 5), mask); in edma_trigger_channel()
668 edma_shadow0_write_array(ecc, SH_ECR, j, mask); in edma_clean_channel()
672 edma_shadow0_write_array(ecc, SH_SECR, j, mask); in edma_clean_channel()
1436 edma_shadow0_write_array(ecc, SH_ICR, bank, BIT(slot)); in dma_irq_handler()
1532 edma_shadow0_write_array(ecc, SH_SECR, j, in dma_ccerr_handler()