Lines Matching refs:ecc
213 struct edma_cc *ecc; member
277 static inline unsigned int edma_read(struct edma_cc *ecc, int offset) in edma_read() argument
279 return (unsigned int)__raw_readl(ecc->base + offset); in edma_read()
282 static inline void edma_write(struct edma_cc *ecc, int offset, int val) in edma_write() argument
284 __raw_writel(val, ecc->base + offset); in edma_write()
287 static inline void edma_modify(struct edma_cc *ecc, int offset, unsigned and, in edma_modify() argument
290 unsigned val = edma_read(ecc, offset); in edma_modify()
294 edma_write(ecc, offset, val); in edma_modify()
297 static inline void edma_and(struct edma_cc *ecc, int offset, unsigned and) in edma_and() argument
299 unsigned val = edma_read(ecc, offset); in edma_and()
302 edma_write(ecc, offset, val); in edma_and()
305 static inline void edma_or(struct edma_cc *ecc, int offset, unsigned or) in edma_or() argument
307 unsigned val = edma_read(ecc, offset); in edma_or()
310 edma_write(ecc, offset, val); in edma_or()
313 static inline unsigned int edma_read_array(struct edma_cc *ecc, int offset, in edma_read_array() argument
316 return edma_read(ecc, offset + (i << 2)); in edma_read_array()
319 static inline void edma_write_array(struct edma_cc *ecc, int offset, int i, in edma_write_array() argument
322 edma_write(ecc, offset + (i << 2), val); in edma_write_array()
325 static inline void edma_modify_array(struct edma_cc *ecc, int offset, int i, in edma_modify_array() argument
328 edma_modify(ecc, offset + (i << 2), and, or); in edma_modify_array()
331 static inline void edma_or_array(struct edma_cc *ecc, int offset, int i, in edma_or_array() argument
334 edma_or(ecc, offset + (i << 2), or); in edma_or_array()
337 static inline void edma_or_array2(struct edma_cc *ecc, int offset, int i, int j, in edma_or_array2() argument
340 edma_or(ecc, offset + ((i * 2 + j) << 2), or); in edma_or_array2()
343 static inline void edma_write_array2(struct edma_cc *ecc, int offset, int i, in edma_write_array2() argument
346 edma_write(ecc, offset + ((i * 2 + j) << 2), val); in edma_write_array2()
349 static inline unsigned int edma_shadow0_read(struct edma_cc *ecc, int offset) in edma_shadow0_read() argument
351 return edma_read(ecc, EDMA_SHADOW0 + offset); in edma_shadow0_read()
354 static inline unsigned int edma_shadow0_read_array(struct edma_cc *ecc, in edma_shadow0_read_array() argument
357 return edma_read(ecc, EDMA_SHADOW0 + offset + (i << 2)); in edma_shadow0_read_array()
360 static inline void edma_shadow0_write(struct edma_cc *ecc, int offset, in edma_shadow0_write() argument
363 edma_write(ecc, EDMA_SHADOW0 + offset, val); in edma_shadow0_write()
366 static inline void edma_shadow0_write_array(struct edma_cc *ecc, int offset, in edma_shadow0_write_array() argument
369 edma_write(ecc, EDMA_SHADOW0 + offset + (i << 2), val); in edma_shadow0_write_array()
372 static inline unsigned int edma_param_read(struct edma_cc *ecc, int offset, in edma_param_read() argument
375 return edma_read(ecc, EDMA_PARM + offset + (param_no << 5)); in edma_param_read()
378 static inline void edma_param_write(struct edma_cc *ecc, int offset, in edma_param_write() argument
381 edma_write(ecc, EDMA_PARM + offset + (param_no << 5), val); in edma_param_write()
384 static inline void edma_param_modify(struct edma_cc *ecc, int offset, in edma_param_modify() argument
387 edma_modify(ecc, EDMA_PARM + offset + (param_no << 5), and, or); in edma_param_modify()
390 static inline void edma_param_and(struct edma_cc *ecc, int offset, int param_no, in edma_param_and() argument
393 edma_and(ecc, EDMA_PARM + offset + (param_no << 5), and); in edma_param_and()
396 static inline void edma_param_or(struct edma_cc *ecc, int offset, int param_no, in edma_param_or() argument
399 edma_or(ecc, EDMA_PARM + offset + (param_no << 5), or); in edma_param_or()
414 static void edma_assign_priority_to_queue(struct edma_cc *ecc, int queue_no, in edma_assign_priority_to_queue() argument
419 edma_modify(ecc, EDMA_QUEPRI, ~(0x7 << bit), ((priority & 0x7) << bit)); in edma_assign_priority_to_queue()
424 struct edma_cc *ecc = echan->ecc; in edma_set_chmap() local
427 if (ecc->chmap_exist) { in edma_set_chmap()
429 edma_write_array(ecc, EDMA_DCHMAP, channel, (slot << 5)); in edma_set_chmap()
435 struct edma_cc *ecc = echan->ecc; in edma_setup_interrupt() local
439 edma_shadow0_write_array(ecc, SH_ICR, channel >> 5, in edma_setup_interrupt()
441 edma_shadow0_write_array(ecc, SH_IESR, channel >> 5, in edma_setup_interrupt()
444 edma_shadow0_write_array(ecc, SH_IECR, channel >> 5, in edma_setup_interrupt()
452 static void edma_write_slot(struct edma_cc *ecc, unsigned slot, in edma_write_slot() argument
456 if (slot >= ecc->num_slots) in edma_write_slot()
458 memcpy_toio(ecc->base + PARM_OFFSET(slot), param, PARM_SIZE); in edma_write_slot()
461 static void edma_read_slot(struct edma_cc *ecc, unsigned slot, in edma_read_slot() argument
465 if (slot >= ecc->num_slots) in edma_read_slot()
467 memcpy_fromio(param, ecc->base + PARM_OFFSET(slot), PARM_SIZE); in edma_read_slot()
485 static int edma_alloc_slot(struct edma_cc *ecc, int slot) in edma_alloc_slot() argument
490 if (ecc->chmap_exist && slot < ecc->num_channels) in edma_alloc_slot()
495 if (ecc->chmap_exist) in edma_alloc_slot()
498 slot = ecc->num_channels; in edma_alloc_slot()
500 slot = find_next_zero_bit(ecc->slot_inuse, in edma_alloc_slot()
501 ecc->num_slots, in edma_alloc_slot()
503 if (slot == ecc->num_slots) in edma_alloc_slot()
505 if (!test_and_set_bit(slot, ecc->slot_inuse)) in edma_alloc_slot()
508 } else if (slot >= ecc->num_slots) { in edma_alloc_slot()
510 } else if (test_and_set_bit(slot, ecc->slot_inuse)) { in edma_alloc_slot()
514 edma_write_slot(ecc, slot, &dummy_paramset); in edma_alloc_slot()
516 return EDMA_CTLR_CHAN(ecc->id, slot); in edma_alloc_slot()
519 static void edma_free_slot(struct edma_cc *ecc, unsigned slot) in edma_free_slot() argument
522 if (slot >= ecc->num_slots) in edma_free_slot()
525 edma_write_slot(ecc, slot, &dummy_paramset); in edma_free_slot()
526 clear_bit(slot, ecc->slot_inuse); in edma_free_slot()
537 static void edma_link(struct edma_cc *ecc, unsigned from, unsigned to) in edma_link() argument
540 dev_warn(ecc->dev, "Ignoring eDMA instance for linking\n"); in edma_link()
544 if (from >= ecc->num_slots || to >= ecc->num_slots) in edma_link()
547 edma_param_modify(ecc, PARM_LINK_BCNTRLD, from, 0xffff0000, in edma_link()
559 static dma_addr_t edma_get_position(struct edma_cc *ecc, unsigned slot, in edma_get_position() argument
568 return edma_read(ecc, offs); in edma_get_position()
579 struct edma_cc *ecc = echan->ecc; in edma_start() local
586 dev_dbg(ecc->dev, "ESR%d %08x\n", j, in edma_start()
587 edma_shadow0_read_array(ecc, SH_ESR, j)); in edma_start()
588 edma_shadow0_write_array(ecc, SH_ESR, j, mask); in edma_start()
591 dev_dbg(ecc->dev, "ER%d %08x\n", j, in edma_start()
592 edma_shadow0_read_array(ecc, SH_ER, j)); in edma_start()
594 edma_write_array(ecc, EDMA_ECR, j, mask); in edma_start()
595 edma_write_array(ecc, EDMA_EMCR, j, mask); in edma_start()
597 edma_shadow0_write_array(ecc, SH_SECR, j, mask); in edma_start()
598 edma_shadow0_write_array(ecc, SH_EESR, j, mask); in edma_start()
599 dev_dbg(ecc->dev, "EER%d %08x\n", j, in edma_start()
600 edma_shadow0_read_array(ecc, SH_EER, j)); in edma_start()
606 struct edma_cc *ecc = echan->ecc; in edma_stop() local
611 edma_shadow0_write_array(ecc, SH_EECR, j, mask); in edma_stop()
612 edma_shadow0_write_array(ecc, SH_ECR, j, mask); in edma_stop()
613 edma_shadow0_write_array(ecc, SH_SECR, j, mask); in edma_stop()
614 edma_write_array(ecc, EDMA_EMCR, j, mask); in edma_stop()
617 edma_shadow0_write_array(ecc, SH_ICR, j, mask); in edma_stop()
619 dev_dbg(ecc->dev, "EER%d %08x\n", j, in edma_stop()
620 edma_shadow0_read_array(ecc, SH_EER, j)); in edma_stop()
636 edma_shadow0_write_array(echan->ecc, SH_EECR, channel >> 5, mask); in edma_pause()
645 edma_shadow0_write_array(echan->ecc, SH_EESR, channel >> 5, mask); in edma_resume()
650 struct edma_cc *ecc = echan->ecc; in edma_trigger_channel() local
654 edma_shadow0_write_array(ecc, SH_ESR, (channel >> 5), mask); in edma_trigger_channel()
656 dev_dbg(ecc->dev, "ESR%d %08x\n", (channel >> 5), in edma_trigger_channel()
657 edma_shadow0_read_array(ecc, SH_ESR, (channel >> 5))); in edma_trigger_channel()
662 struct edma_cc *ecc = echan->ecc; in edma_clean_channel() local
667 dev_dbg(ecc->dev, "EMR%d %08x\n", j, edma_read_array(ecc, EDMA_EMR, j)); in edma_clean_channel()
668 edma_shadow0_write_array(ecc, SH_ECR, j, mask); in edma_clean_channel()
670 edma_write_array(ecc, EDMA_EMCR, j, mask); in edma_clean_channel()
672 edma_shadow0_write_array(ecc, SH_SECR, j, mask); in edma_clean_channel()
673 edma_write(ecc, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0)); in edma_clean_channel()
680 struct edma_cc *ecc = echan->ecc; in edma_assign_channel_eventq() local
686 eventq_no = ecc->default_queue; in edma_assign_channel_eventq()
687 if (eventq_no >= ecc->num_tc) in edma_assign_channel_eventq()
691 edma_modify_array(ecc, EDMA_DMAQNUM, (channel >> 3), ~(0x7 << bit), in edma_assign_channel_eventq()
698 struct edma_cc *ecc = echan->ecc; in edma_alloc_channel() local
702 edma_or_array2(ecc, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f)); in edma_alloc_channel()
745 struct edma_cc *ecc = echan->ecc; in edma_execute() local
770 edma_write_slot(ecc, echan->slot[i], &edesc->pset[j].param); in edma_execute()
795 edma_link(ecc, echan->slot[i], echan->slot[i + 1]); in edma_execute()
807 edma_link(ecc, echan->slot[nslots - 1], echan->slot[1]); in edma_execute()
809 edma_link(ecc, echan->slot[nslots - 1], in edma_execute()
810 echan->ecc->dummy_slot); in edma_execute()
1078 edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY); in edma_prep_slave_sg()
1194 echan->slot[1] = edma_alloc_slot(echan->ecc, in edma_prep_dma_memcpy()
1295 edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY); in edma_prep_dma_cyclic()
1402 struct edma_cc *ecc = data; in dma_irq_handler() local
1408 ctlr = ecc->id; in dma_irq_handler()
1412 dev_vdbg(ecc->dev, "dma_irq_handler\n"); in dma_irq_handler()
1414 sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 0); in dma_irq_handler()
1416 sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 1); in dma_irq_handler()
1419 sh_ier = edma_shadow0_read_array(ecc, SH_IER, 1); in dma_irq_handler()
1422 sh_ier = edma_shadow0_read_array(ecc, SH_IER, 0); in dma_irq_handler()
1436 edma_shadow0_write_array(ecc, SH_ICR, bank, BIT(slot)); in dma_irq_handler()
1437 edma_completion_handler(&ecc->slave_chans[channel]); in dma_irq_handler()
1441 edma_shadow0_write(ecc, SH_IEVAL, 1); in dma_irq_handler()
1447 struct edma_cc *ecc = echan->ecc; in edma_error_handler() local
1456 edma_read_slot(ecc, echan->slot[0], &p); in edma_error_handler()
1486 static inline bool edma_error_pending(struct edma_cc *ecc) in edma_error_pending() argument
1488 if (edma_read_array(ecc, EDMA_EMR, 0) || in edma_error_pending()
1489 edma_read_array(ecc, EDMA_EMR, 1) || in edma_error_pending()
1490 edma_read(ecc, EDMA_QEMR) || edma_read(ecc, EDMA_CCERR)) in edma_error_pending()
1499 struct edma_cc *ecc = data; in dma_ccerr_handler() local
1505 ctlr = ecc->id; in dma_ccerr_handler()
1509 dev_vdbg(ecc->dev, "dma_ccerr_handler\n"); in dma_ccerr_handler()
1511 if (!edma_error_pending(ecc)) in dma_ccerr_handler()
1519 val = edma_read_array(ecc, EDMA_EMR, j); in dma_ccerr_handler()
1523 dev_dbg(ecc->dev, "EMR%d 0x%08x\n", j, val); in dma_ccerr_handler()
1530 edma_write_array(ecc, EDMA_EMCR, j, BIT(i)); in dma_ccerr_handler()
1532 edma_shadow0_write_array(ecc, SH_SECR, j, in dma_ccerr_handler()
1534 edma_error_handler(&ecc->slave_chans[k]); in dma_ccerr_handler()
1538 val = edma_read(ecc, EDMA_QEMR); in dma_ccerr_handler()
1540 dev_dbg(ecc->dev, "QEMR 0x%02x\n", val); in dma_ccerr_handler()
1542 edma_write(ecc, EDMA_QEMCR, val); in dma_ccerr_handler()
1543 edma_shadow0_write(ecc, SH_QSECR, val); in dma_ccerr_handler()
1546 val = edma_read(ecc, EDMA_CCERR); in dma_ccerr_handler()
1548 dev_warn(ecc->dev, "CCERR 0x%08x\n", val); in dma_ccerr_handler()
1550 edma_write(ecc, EDMA_CCERRCLR, val); in dma_ccerr_handler()
1553 if (!edma_error_pending(ecc)) in dma_ccerr_handler()
1559 edma_write(ecc, EDMA_EEVAL, 1); in dma_ccerr_handler()
1593 struct edma_cc *ecc = echan->ecc; in edma_alloc_chan_resources() local
1594 struct device *dev = ecc->dev; in edma_alloc_chan_resources()
1600 } else if (ecc->tc_list) { in edma_alloc_chan_resources()
1602 echan->tc = &ecc->tc_list[ecc->info->default_queue]; in edma_alloc_chan_resources()
1610 echan->slot[0] = edma_alloc_slot(ecc, echan->ch_num); in edma_alloc_chan_resources()
1638 struct device *dev = echan->ecc->dev; in edma_free_chan_resources()
1649 edma_free_slot(echan->ecc, echan->slot[i]); in edma_free_chan_resources()
1655 edma_set_chmap(echan, echan->ecc->dummy_slot); in edma_free_chan_resources()
1694 pos = edma_get_position(edesc->echan->ecc, edesc->echan->slot[0], dst); in edma_residue()
1772 static void edma_dma_init(struct edma_cc *ecc, bool legacy_mode) in edma_dma_init() argument
1774 struct dma_device *s_ddev = &ecc->dma_slave; in edma_dma_init()
1776 s32 *memcpy_channels = ecc->info->memcpy_channels; in edma_dma_init()
1782 if (ecc->legacy_mode && !memcpy_channels) { in edma_dma_init()
1783 dev_warn(ecc->dev, in edma_dma_init()
1807 s_ddev->dev = ecc->dev; in edma_dma_init()
1811 m_ddev = devm_kzalloc(ecc->dev, sizeof(*m_ddev), GFP_KERNEL); in edma_dma_init()
1812 ecc->dma_memcpy = m_ddev; in edma_dma_init()
1832 m_ddev->dev = ecc->dev; in edma_dma_init()
1834 } else if (!ecc->legacy_mode) { in edma_dma_init()
1835 dev_info(ecc->dev, "memcpy is disabled\n"); in edma_dma_init()
1838 for (i = 0; i < ecc->num_channels; i++) { in edma_dma_init()
1839 struct edma_chan *echan = &ecc->slave_chans[i]; in edma_dma_init()
1840 echan->ch_num = EDMA_CTLR_CHAN(ecc->id, i); in edma_dma_init()
1841 echan->ecc = ecc; in edma_dma_init()
1856 struct edma_cc *ecc) in edma_setup_from_hw() argument
1863 cccfg = edma_read(ecc, EDMA_CCCFG); in edma_setup_from_hw()
1866 ecc->num_region = BIT(value); in edma_setup_from_hw()
1869 ecc->num_channels = BIT(value + 1); in edma_setup_from_hw()
1872 ecc->num_qchannels = value * 2; in edma_setup_from_hw()
1875 ecc->num_slots = BIT(value + 4); in edma_setup_from_hw()
1878 ecc->num_tc = value + 1; in edma_setup_from_hw()
1880 ecc->chmap_exist = (cccfg & CHMAP_EXIST) ? true : false; in edma_setup_from_hw()
1883 dev_dbg(dev, "num_region: %u\n", ecc->num_region); in edma_setup_from_hw()
1884 dev_dbg(dev, "num_channels: %u\n", ecc->num_channels); in edma_setup_from_hw()
1885 dev_dbg(dev, "num_qchannels: %u\n", ecc->num_qchannels); in edma_setup_from_hw()
1886 dev_dbg(dev, "num_slots: %u\n", ecc->num_slots); in edma_setup_from_hw()
1887 dev_dbg(dev, "num_tc: %u\n", ecc->num_tc); in edma_setup_from_hw()
1888 dev_dbg(dev, "chmap_exist: %s\n", ecc->chmap_exist ? "yes" : "no"); in edma_setup_from_hw()
1904 queue_priority_map = devm_kcalloc(dev, ecc->num_tc + 1, sizeof(s8), in edma_setup_from_hw()
1909 for (i = 0; i < ecc->num_tc; i++) { in edma_setup_from_hw()
2070 struct edma_cc *ecc = ofdma->of_dma_data; in of_edma_xlate() local
2075 if (!ecc || dma_spec->args_count < 1) in of_edma_xlate()
2078 for (i = 0; i < ecc->num_channels; i++) { in of_edma_xlate()
2079 echan = &ecc->slave_chans[i]; in of_edma_xlate()
2089 if (echan->ecc->legacy_mode && dma_spec->args_count == 1) in of_edma_xlate()
2092 if (!echan->ecc->legacy_mode && dma_spec->args_count == 2 && in of_edma_xlate()
2093 dma_spec->args[1] < echan->ecc->num_tc) { in of_edma_xlate()
2094 echan->tc = &echan->ecc->tc_list[dma_spec->args[1]]; in of_edma_xlate()
2130 struct edma_cc *ecc; in edma_probe() local
2162 ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL); in edma_probe()
2163 if (!ecc) { in edma_probe()
2168 ecc->dev = dev; in edma_probe()
2169 ecc->id = pdev->id; in edma_probe()
2170 ecc->legacy_mode = legacy_mode; in edma_probe()
2172 if (ecc->id < 0) in edma_probe()
2173 ecc->id = 0; in edma_probe()
2184 ecc->base = devm_ioremap_resource(dev, mem); in edma_probe()
2185 if (IS_ERR(ecc->base)) in edma_probe()
2186 return PTR_ERR(ecc->base); in edma_probe()
2188 platform_set_drvdata(pdev, ecc); in edma_probe()
2191 ret = edma_setup_from_hw(dev, info, ecc); in edma_probe()
2196 ecc->slave_chans = devm_kcalloc(dev, ecc->num_channels, in edma_probe()
2197 sizeof(*ecc->slave_chans), GFP_KERNEL); in edma_probe()
2198 if (!ecc->slave_chans) in edma_probe()
2201 ecc->slot_inuse = devm_kcalloc(dev, BITS_TO_LONGS(ecc->num_slots), in edma_probe()
2203 if (!ecc->slot_inuse) in edma_probe()
2206 ecc->default_queue = info->default_queue; in edma_probe()
2208 for (i = 0; i < ecc->num_slots; i++) in edma_probe()
2209 edma_write_slot(ecc, i, &dummy_paramset); in edma_probe()
2218 set_bits(off, ln, ecc->slot_inuse); in edma_probe()
2239 ecc); in edma_probe()
2254 ecc); in edma_probe()
2261 ecc->dummy_slot = edma_alloc_slot(ecc, EDMA_SLOT_ANY); in edma_probe()
2262 if (ecc->dummy_slot < 0) { in edma_probe()
2264 return ecc->dummy_slot; in edma_probe()
2269 if (!ecc->legacy_mode) { in edma_probe()
2273 ecc->tc_list = devm_kcalloc(dev, ecc->num_tc, in edma_probe()
2274 sizeof(*ecc->tc_list), GFP_KERNEL); in edma_probe()
2275 if (!ecc->tc_list) in edma_probe()
2281 if (ret || i == ecc->num_tc) in edma_probe()
2284 ecc->tc_list[i].node = tc_args.np; in edma_probe()
2285 ecc->tc_list[i].id = i; in edma_probe()
2296 edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0], in edma_probe()
2299 for (i = 0; i < ecc->num_region; i++) { in edma_probe()
2300 edma_write_array2(ecc, EDMA_DRAE, i, 0, 0x0); in edma_probe()
2301 edma_write_array2(ecc, EDMA_DRAE, i, 1, 0x0); in edma_probe()
2302 edma_write_array(ecc, EDMA_QRAE, i, 0x0); in edma_probe()
2304 ecc->info = info; in edma_probe()
2307 edma_dma_init(ecc, legacy_mode); in edma_probe()
2309 for (i = 0; i < ecc->num_channels; i++) { in edma_probe()
2311 edma_assign_channel_eventq(&ecc->slave_chans[i], in edma_probe()
2314 edma_set_chmap(&ecc->slave_chans[i], ecc->dummy_slot); in edma_probe()
2317 ret = dma_async_device_register(&ecc->dma_slave); in edma_probe()
2323 if (ecc->dma_memcpy) { in edma_probe()
2324 ret = dma_async_device_register(ecc->dma_memcpy); in edma_probe()
2328 dma_async_device_unregister(&ecc->dma_slave); in edma_probe()
2334 of_dma_controller_register(node, of_edma_xlate, ecc); in edma_probe()
2341 edma_free_slot(ecc, ecc->dummy_slot); in edma_probe()
2348 struct edma_cc *ecc = dev_get_drvdata(dev); in edma_remove() local
2352 dma_async_device_unregister(&ecc->dma_slave); in edma_remove()
2353 if (ecc->dma_memcpy) in edma_remove()
2354 dma_async_device_unregister(ecc->dma_memcpy); in edma_remove()
2355 edma_free_slot(ecc, ecc->dummy_slot); in edma_remove()
2363 struct edma_cc *ecc = dev_get_drvdata(dev); in edma_pm_suspend() local
2364 struct edma_chan *echan = ecc->slave_chans; in edma_pm_suspend()
2367 for (i = 0; i < ecc->num_channels; i++) { in edma_pm_suspend()
2379 struct edma_cc *ecc = dev_get_drvdata(dev); in edma_pm_resume() local
2380 struct edma_chan *echan = ecc->slave_chans; in edma_pm_resume()
2384 queue_priority_mapping = ecc->info->queue_priority_mapping; in edma_pm_resume()
2388 edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0], in edma_pm_resume()
2391 for (i = 0; i < ecc->num_channels; i++) { in edma_pm_resume()
2394 edma_or_array2(ecc, EDMA_DRAE, 0, i >> 5, in edma_pm_resume()