Lines Matching refs:reg_width
772 unsigned int reg_width; in dwc_prep_slave_sg() local
790 reg_width = __ffs(sconfig->dst_addr_width); in dwc_prep_slave_sg()
793 | DWC_CTLL_DST_WIDTH(reg_width) in dwc_prep_slave_sg()
847 reg_width = __ffs(sconfig->src_addr_width); in dwc_prep_slave_sg()
850 | DWC_CTLL_SRC_WIDTH(reg_width) in dwc_prep_slave_sg()
877 if ((len >> reg_width) > dwc->block_size) { in dwc_prep_slave_sg()
878 dlen = dwc->block_size << reg_width; in dwc_prep_slave_sg()
885 desc->lli.ctlhi = dlen >> reg_width; in dwc_prep_slave_sg()
1325 unsigned int reg_width; in dw_dma_cyclic_prep() local
1361 reg_width = __ffs(sconfig->dst_addr_width); in dw_dma_cyclic_prep()
1363 reg_width = __ffs(sconfig->src_addr_width); in dw_dma_cyclic_prep()
1368 if (period_len > (dwc->block_size << reg_width)) in dw_dma_cyclic_prep()
1370 if (unlikely(period_len & ((1 << reg_width) - 1))) in dw_dma_cyclic_prep()
1372 if (unlikely(buf_addr & ((1 << reg_width) - 1))) in dw_dma_cyclic_prep()
1398 | DWC_CTLL_DST_WIDTH(reg_width) in dw_dma_cyclic_prep()
1399 | DWC_CTLL_SRC_WIDTH(reg_width) in dw_dma_cyclic_prep()
1413 | DWC_CTLL_SRC_WIDTH(reg_width) in dw_dma_cyclic_prep()
1414 | DWC_CTLL_DST_WIDTH(reg_width) in dw_dma_cyclic_prep()
1428 desc->lli.ctlhi = (period_len >> reg_width); in dw_dma_cyclic_prep()