238 	u32		mbr_cfg;	/* Configuration Register */  member
375 	at_xdmac_chan_write(atchan, AT_XDMAC_CC, first->lld.mbr_cfg);  in at_xdmac_start_xfer()
703 		desc->lld.mbr_cfg = (atchan->cfg & ~AT_XDMAC_CC_DWIDTH_MASK) |  in at_xdmac_prep_slave_sg()
787 		desc->lld.mbr_cfg = atchan->cfg;  in at_xdmac_prep_dma_cyclic()
791 			| period_len >> at_xdmac_get_dwidth(desc->lld.mbr_cfg);  in at_xdmac_prep_dma_cyclic()
921 	desc->lld.mbr_cfg = chan_cc;  in at_xdmac_interleaved_queue_desc()
926 		desc->lld.mbr_ubc, desc->lld.mbr_cfg);  in at_xdmac_interleaved_queue_desc()
1104 		desc->lld.mbr_cfg = chan_cc;  in at_xdmac_prep_dma_memcpy()
1108 			 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc, desc->lld.mbr_cfg);  in at_xdmac_prep_dma_memcpy()
1183 	desc->lld.mbr_cfg = chan_cc;  in at_xdmac_memset_create_desc()
1188 		desc->lld.mbr_cfg);  in at_xdmac_memset_create_desc()
1419 	if ((desc->lld.mbr_cfg & mask) == value) {  in at_xdmac_tx_status()
1468 		dwidth = at_xdmac_get_dwidth(desc->lld.mbr_cfg);  in at_xdmac_tx_status()