Lines Matching refs:ccfg
196 u32 ccfg; member
362 struct pl08x_phy_chan *phychan, const u32 *lli, u32 ccfg) in pl08x_write_lli() argument
370 lli[PL080S_LLI_CCTL2], ccfg); in pl08x_write_lli()
376 lli[PL080_LLI_LLI], lli[PL080_LLI_CCTL], ccfg); in pl08x_write_lli()
387 writel(ccfg, phychan->reg_config); in pl08x_write_lli()
412 pl08x_write_lli(pl08x, phychan, &txd->llis_va[0], txd->ccfg); in pl08x_start_next_txd()
1006 u32 fc = (txd->ccfg & PL080_CONFIG_FLOW_CONTROL_MASK) >> in pl08x_fill_llis_for_desc()
1413 txd->ccfg = PL080_CONFIG_ERR_IRQ_MASK | in pl08x_get_txd()
1453 txd->ccfg |= PL080_FLOW_MEM2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT; in pl08x_prep_dma_memcpy()
1535 txd->ccfg |= tmp << PL080_CONFIG_FLOW_CONTROL_SHIFT; in pl08x_init_txd()
1551 txd->ccfg |= plchan->signal << PL080_CONFIG_DST_SEL_SHIFT; in pl08x_init_txd()
1553 txd->ccfg |= plchan->signal << PL080_CONFIG_SRC_SEL_SHIFT; in pl08x_init_txd()