Lines Matching refs:handle
78 #define AE(handle, ae) handle->hal_handle->aes[ae] argument
111 void qat_hal_set_live_ctx(struct icp_qat_fw_loader_handle *handle, in qat_hal_set_live_ctx() argument
114 AE(handle, ae).live_ctx_mask = ctx_mask; in qat_hal_set_live_ctx()
118 static int qat_hal_rd_ae_csr(struct icp_qat_fw_loader_handle *handle, in qat_hal_rd_ae_csr() argument
125 *value = GET_AE_CSR(handle, ae, csr); in qat_hal_rd_ae_csr()
126 if (!(GET_AE_CSR(handle, ae, LOCAL_CSR_STATUS) & LCS_STATUS)) in qat_hal_rd_ae_csr()
134 static int qat_hal_wr_ae_csr(struct icp_qat_fw_loader_handle *handle, in qat_hal_wr_ae_csr() argument
141 SET_AE_CSR(handle, ae, csr, value); in qat_hal_wr_ae_csr()
142 if (!(GET_AE_CSR(handle, ae, LOCAL_CSR_STATUS) & LCS_STATUS)) in qat_hal_wr_ae_csr()
150 static void qat_hal_get_wakeup_event(struct icp_qat_fw_loader_handle *handle, in qat_hal_get_wakeup_event() argument
156 qat_hal_rd_ae_csr(handle, ae, CSR_CTX_POINTER, &cur_ctx); in qat_hal_get_wakeup_event()
157 qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, ctx); in qat_hal_get_wakeup_event()
158 qat_hal_rd_ae_csr(handle, ae, CTX_WAKEUP_EVENTS_INDIRECT, events); in qat_hal_get_wakeup_event()
159 qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, cur_ctx); in qat_hal_get_wakeup_event()
162 static int qat_hal_wait_cycles(struct icp_qat_fw_loader_handle *handle, in qat_hal_wait_cycles() argument
171 qat_hal_rd_ae_csr(handle, ae, PROFILE_COUNT, &base_cnt); in qat_hal_wait_cycles()
175 qat_hal_rd_ae_csr(handle, ae, ACTIVE_CTX_STATUS, &csr); in qat_hal_wait_cycles()
177 qat_hal_rd_ae_csr(handle, ae, PROFILE_COUNT, &cur_cnt); in qat_hal_wait_cycles()
198 int qat_hal_set_ae_ctx_mode(struct icp_qat_fw_loader_handle *handle, in qat_hal_set_ae_ctx_mode() argument
209 qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &csr); in qat_hal_set_ae_ctx_mode()
214 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, new_csr); in qat_hal_set_ae_ctx_mode()
218 int qat_hal_set_ae_nn_mode(struct icp_qat_fw_loader_handle *handle, in qat_hal_set_ae_nn_mode() argument
223 qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &csr); in qat_hal_set_ae_nn_mode()
231 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, new_csr); in qat_hal_set_ae_nn_mode()
236 int qat_hal_set_ae_lm_mode(struct icp_qat_fw_loader_handle *handle, in qat_hal_set_ae_lm_mode() argument
242 qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &csr); in qat_hal_set_ae_lm_mode()
261 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, new_csr); in qat_hal_set_ae_lm_mode()
314 void qat_hal_reset(struct icp_qat_fw_loader_handle *handle) in qat_hal_reset() argument
318 ae_reset_csr = GET_GLB_CSR(handle, ICP_RESET); in qat_hal_reset()
319 ae_reset_csr |= handle->hal_handle->ae_mask << RST_CSR_AE_LSB; in qat_hal_reset()
320 ae_reset_csr |= handle->hal_handle->slice_mask << RST_CSR_QAT_LSB; in qat_hal_reset()
321 SET_GLB_CSR(handle, ICP_RESET, ae_reset_csr); in qat_hal_reset()
324 static void qat_hal_wr_indr_csr(struct icp_qat_fw_loader_handle *handle, in qat_hal_wr_indr_csr() argument
330 qat_hal_rd_ae_csr(handle, ae, CSR_CTX_POINTER, &cur_ctx); in qat_hal_wr_indr_csr()
335 qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, ctx); in qat_hal_wr_indr_csr()
336 qat_hal_wr_ae_csr(handle, ae, ae_csr, csr_val); in qat_hal_wr_indr_csr()
339 qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, cur_ctx); in qat_hal_wr_indr_csr()
342 static void qat_hal_rd_indr_csr(struct icp_qat_fw_loader_handle *handle, in qat_hal_rd_indr_csr() argument
348 qat_hal_rd_ae_csr(handle, ae, CSR_CTX_POINTER, &cur_ctx); in qat_hal_rd_indr_csr()
349 qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, ctx); in qat_hal_rd_indr_csr()
350 qat_hal_rd_ae_csr(handle, ae, ae_csr, csr_val); in qat_hal_rd_indr_csr()
351 qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, cur_ctx); in qat_hal_rd_indr_csr()
354 static void qat_hal_put_sig_event(struct icp_qat_fw_loader_handle *handle, in qat_hal_put_sig_event() argument
360 qat_hal_rd_ae_csr(handle, ae, CSR_CTX_POINTER, &cur_ctx); in qat_hal_put_sig_event()
364 qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, ctx); in qat_hal_put_sig_event()
365 qat_hal_wr_ae_csr(handle, ae, CTX_SIG_EVENTS_INDIRECT, events); in qat_hal_put_sig_event()
367 qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, cur_ctx); in qat_hal_put_sig_event()
370 static void qat_hal_put_wakeup_event(struct icp_qat_fw_loader_handle *handle, in qat_hal_put_wakeup_event() argument
376 qat_hal_rd_ae_csr(handle, ae, CSR_CTX_POINTER, &cur_ctx); in qat_hal_put_wakeup_event()
380 qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, ctx); in qat_hal_put_wakeup_event()
381 qat_hal_wr_ae_csr(handle, ae, CTX_WAKEUP_EVENTS_INDIRECT, in qat_hal_put_wakeup_event()
384 qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, cur_ctx); in qat_hal_put_wakeup_event()
387 static int qat_hal_check_ae_alive(struct icp_qat_fw_loader_handle *handle) in qat_hal_check_ae_alive() argument
393 for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) { in qat_hal_check_ae_alive()
394 if (!(handle->hal_handle->ae_mask & (1 << ae))) in qat_hal_check_ae_alive()
397 qat_hal_rd_ae_csr(handle, ae, PROFILE_COUNT, in qat_hal_check_ae_alive()
402 qat_hal_rd_ae_csr(handle, ae, PROFILE_COUNT, in qat_hal_check_ae_alive()
416 static void qat_hal_reset_timestamp(struct icp_qat_fw_loader_handle *handle) in qat_hal_reset_timestamp() argument
422 misc_ctl = GET_GLB_CSR(handle, MISC_CONTROL); in qat_hal_reset_timestamp()
424 SET_GLB_CSR(handle, MISC_CONTROL, misc_ctl & in qat_hal_reset_timestamp()
427 for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) { in qat_hal_reset_timestamp()
428 if (!(handle->hal_handle->ae_mask & (1 << ae))) in qat_hal_reset_timestamp()
430 qat_hal_wr_ae_csr(handle, ae, TIMESTAMP_LOW, 0); in qat_hal_reset_timestamp()
431 qat_hal_wr_ae_csr(handle, ae, TIMESTAMP_HIGH, 0); in qat_hal_reset_timestamp()
434 SET_GLB_CSR(handle, MISC_CONTROL, misc_ctl | MC_TIMESTAMP_ENABLE); in qat_hal_reset_timestamp()
441 static int qat_hal_init_esram(struct icp_qat_fw_loader_handle *handle) in qat_hal_init_esram() argument
443 void __iomem *csr_addr = handle->hal_ep_csr_addr_v + in qat_hal_init_esram()
456 qat_hal_wait_cycles(handle, 0, ESRAM_AUTO_INIT_USED_CYCLES, 0); in qat_hal_init_esram()
467 int qat_hal_clr_reset(struct icp_qat_fw_loader_handle *handle) in qat_hal_clr_reset() argument
476 ae_reset_csr = GET_GLB_CSR(handle, ICP_RESET); in qat_hal_clr_reset()
477 ae_reset_csr &= ~(handle->hal_handle->ae_mask << RST_CSR_AE_LSB); in qat_hal_clr_reset()
478 ae_reset_csr &= ~(handle->hal_handle->slice_mask << RST_CSR_QAT_LSB); in qat_hal_clr_reset()
480 SET_GLB_CSR(handle, ICP_RESET, ae_reset_csr); in qat_hal_clr_reset()
483 csr = GET_GLB_CSR(handle, ICP_RESET); in qat_hal_clr_reset()
484 } while ((handle->hal_handle->ae_mask | in qat_hal_clr_reset()
485 (handle->hal_handle->slice_mask << RST_CSR_QAT_LSB)) & csr); in qat_hal_clr_reset()
487 clk_csr = GET_GLB_CSR(handle, ICP_GLOBAL_CLK_ENABLE); in qat_hal_clr_reset()
488 clk_csr |= handle->hal_handle->ae_mask << 0; in qat_hal_clr_reset()
489 clk_csr |= handle->hal_handle->slice_mask << 20; in qat_hal_clr_reset()
490 SET_GLB_CSR(handle, ICP_GLOBAL_CLK_ENABLE, clk_csr); in qat_hal_clr_reset()
491 if (qat_hal_check_ae_alive(handle)) in qat_hal_clr_reset()
495 for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) { in qat_hal_clr_reset()
496 if (!(handle->hal_handle->ae_mask & (1 << ae))) in qat_hal_clr_reset()
498 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, in qat_hal_clr_reset()
500 qat_hal_wr_indr_csr(handle, ae, ICP_QAT_UCLO_AE_ALL_CTX, in qat_hal_clr_reset()
502 handle->hal_handle->upc_mask & in qat_hal_clr_reset()
504 qat_hal_wr_ae_csr(handle, ae, CTX_ARB_CNTL, INIT_CTX_ARB_VALUE); in qat_hal_clr_reset()
505 qat_hal_wr_ae_csr(handle, ae, CC_ENABLE, INIT_CCENABLE_VALUE); in qat_hal_clr_reset()
506 qat_hal_put_wakeup_event(handle, ae, in qat_hal_clr_reset()
509 qat_hal_put_sig_event(handle, ae, in qat_hal_clr_reset()
513 if (qat_hal_init_esram(handle)) in qat_hal_clr_reset()
515 if (qat_hal_wait_cycles(handle, 0, SHRAM_INIT_CYCLES, 0)) in qat_hal_clr_reset()
517 qat_hal_reset_timestamp(handle); in qat_hal_clr_reset()
525 static void qat_hal_disable_ctx(struct icp_qat_fw_loader_handle *handle, in qat_hal_disable_ctx() argument
530 qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx); in qat_hal_disable_ctx()
533 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx); in qat_hal_disable_ctx()
566 void qat_hal_wr_uwords(struct icp_qat_fw_loader_handle *handle, in qat_hal_wr_uwords() argument
573 qat_hal_rd_ae_csr(handle, ae, USTORE_ADDRESS, &ustore_addr); in qat_hal_wr_uwords()
575 qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, uaddr); in qat_hal_wr_uwords()
583 qat_hal_wr_ae_csr(handle, ae, USTORE_DATA_LOWER, uwrd_lo); in qat_hal_wr_uwords()
584 qat_hal_wr_ae_csr(handle, ae, USTORE_DATA_UPPER, uwrd_hi); in qat_hal_wr_uwords()
586 qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, ustore_addr); in qat_hal_wr_uwords()
589 static void qat_hal_enable_ctx(struct icp_qat_fw_loader_handle *handle, in qat_hal_enable_ctx() argument
594 qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx); in qat_hal_enable_ctx()
598 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx); in qat_hal_enable_ctx()
601 static int qat_hal_clear_gpr(struct icp_qat_fw_loader_handle *handle) in qat_hal_clear_gpr() argument
611 for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) { in qat_hal_clear_gpr()
612 if (!(handle->hal_handle->ae_mask & (1 << ae))) in qat_hal_clear_gpr()
615 qat_hal_init_rd_xfer(handle, ae, 0, ICP_SR_RD_ABS, in qat_hal_clear_gpr()
617 qat_hal_init_rd_xfer(handle, ae, 0, ICP_DR_RD_ABS, in qat_hal_clear_gpr()
620 qat_hal_rd_ae_csr(handle, ae, AE_MISC_CONTROL, &csr_val); in qat_hal_clear_gpr()
622 qat_hal_wr_ae_csr(handle, ae, AE_MISC_CONTROL, csr_val); in qat_hal_clear_gpr()
623 qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &csr_val); in qat_hal_clear_gpr()
626 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, csr_val); in qat_hal_clear_gpr()
627 qat_hal_wr_uwords(handle, ae, 0, ARRAY_SIZE(inst), in qat_hal_clear_gpr()
629 qat_hal_wr_indr_csr(handle, ae, ctx_mask, CTX_STS_INDIRECT, in qat_hal_clear_gpr()
630 handle->hal_handle->upc_mask & in qat_hal_clear_gpr()
632 qat_hal_rd_ae_csr(handle, ae, ACTIVE_CTX_STATUS, &savctx); in qat_hal_clear_gpr()
633 qat_hal_wr_ae_csr(handle, ae, ACTIVE_CTX_STATUS, 0); in qat_hal_clear_gpr()
634 qat_hal_put_wakeup_event(handle, ae, ctx_mask, XCWE_VOLUNTARY); in qat_hal_clear_gpr()
635 qat_hal_wr_indr_csr(handle, ae, ctx_mask, in qat_hal_clear_gpr()
637 qat_hal_wr_ae_csr(handle, ae, CTX_SIG_EVENTS_ACTIVE, 0); in qat_hal_clear_gpr()
638 qat_hal_enable_ctx(handle, ae, ctx_mask); in qat_hal_clear_gpr()
640 for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) { in qat_hal_clear_gpr()
641 if (!(handle->hal_handle->ae_mask & (1 << ae))) in qat_hal_clear_gpr()
645 ret = qat_hal_wait_cycles(handle, ae, 20, 1); in qat_hal_clear_gpr()
652 qat_hal_disable_ctx(handle, ae, ctx_mask); in qat_hal_clear_gpr()
653 qat_hal_wr_ae_csr(handle, ae, ACTIVE_CTX_STATUS, in qat_hal_clear_gpr()
655 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, in qat_hal_clear_gpr()
657 qat_hal_wr_indr_csr(handle, ae, ctx_mask, CTX_STS_INDIRECT, in qat_hal_clear_gpr()
658 handle->hal_handle->upc_mask & in qat_hal_clear_gpr()
660 qat_hal_wr_ae_csr(handle, ae, CTX_ARB_CNTL, INIT_CTX_ARB_VALUE); in qat_hal_clear_gpr()
661 qat_hal_wr_ae_csr(handle, ae, CC_ENABLE, INIT_CCENABLE_VALUE); in qat_hal_clear_gpr()
662 qat_hal_put_wakeup_event(handle, ae, ctx_mask, in qat_hal_clear_gpr()
664 qat_hal_put_sig_event(handle, ae, ctx_mask, in qat_hal_clear_gpr()
678 struct icp_qat_fw_loader_handle *handle; in qat_hal_init() local
686 handle = kzalloc(sizeof(*handle), GFP_KERNEL); in qat_hal_init()
687 if (!handle) in qat_hal_init()
690 handle->hal_cap_g_ctl_csr_addr_v = misc_bar->virt_addr + in qat_hal_init()
692 handle->hal_cap_ae_xfer_csr_addr_v = misc_bar->virt_addr + in qat_hal_init()
694 handle->hal_ep_csr_addr_v = misc_bar->virt_addr + in qat_hal_init()
696 handle->hal_cap_ae_local_csr_addr_v = in qat_hal_init()
697 handle->hal_cap_ae_xfer_csr_addr_v + LOCAL_TO_XFER_REG_OFFSET; in qat_hal_init()
698 handle->hal_sram_addr_v = sram_bar->virt_addr; in qat_hal_init()
699 handle->hal_handle = kzalloc(sizeof(*handle->hal_handle), GFP_KERNEL); in qat_hal_init()
700 if (!handle->hal_handle) in qat_hal_init()
702 handle->hal_handle->revision_id = accel_dev->accel_pci_dev.revid; in qat_hal_init()
703 handle->hal_handle->ae_mask = hw_data->ae_mask; in qat_hal_init()
704 handle->hal_handle->slice_mask = hw_data->accel_mask; in qat_hal_init()
706 handle->hal_handle->upc_mask = 0x1ffff; in qat_hal_init()
707 handle->hal_handle->max_ustore = 0x4000; in qat_hal_init()
711 handle->hal_handle->aes[ae].free_addr = 0; in qat_hal_init()
712 handle->hal_handle->aes[ae].free_size = in qat_hal_init()
713 handle->hal_handle->max_ustore; in qat_hal_init()
714 handle->hal_handle->aes[ae].ustore_size = in qat_hal_init()
715 handle->hal_handle->max_ustore; in qat_hal_init()
716 handle->hal_handle->aes[ae].live_ctx_mask = in qat_hal_init()
720 handle->hal_handle->ae_max_num = max_en_ae_id + 1; in qat_hal_init()
722 if (qat_hal_clr_reset(handle)) { in qat_hal_init()
726 if (qat_hal_clear_gpr(handle)) in qat_hal_init()
729 for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) { in qat_hal_init()
734 qat_hal_rd_ae_csr(handle, ae, SIGNATURE_ENABLE, &csr_val); in qat_hal_init()
736 qat_hal_wr_ae_csr(handle, ae, SIGNATURE_ENABLE, csr_val); in qat_hal_init()
738 accel_dev->fw_loader->fw_loader = handle; in qat_hal_init()
742 kfree(handle->hal_handle); in qat_hal_init()
744 kfree(handle); in qat_hal_init()
748 void qat_hal_deinit(struct icp_qat_fw_loader_handle *handle) in qat_hal_deinit() argument
750 if (!handle) in qat_hal_deinit()
752 kfree(handle->hal_handle); in qat_hal_deinit()
753 kfree(handle); in qat_hal_deinit()
756 void qat_hal_start(struct icp_qat_fw_loader_handle *handle, unsigned char ae, in qat_hal_start() argument
759 qat_hal_put_wakeup_event(handle, ae, (~ctx_mask) & in qat_hal_start()
761 qat_hal_enable_ctx(handle, ae, ctx_mask); in qat_hal_start()
764 void qat_hal_stop(struct icp_qat_fw_loader_handle *handle, unsigned char ae, in qat_hal_stop() argument
767 qat_hal_disable_ctx(handle, ae, ctx_mask); in qat_hal_stop()
770 void qat_hal_set_pc(struct icp_qat_fw_loader_handle *handle, in qat_hal_set_pc() argument
773 qat_hal_wr_indr_csr(handle, ae, ctx_mask, CTX_STS_INDIRECT, in qat_hal_set_pc()
774 handle->hal_handle->upc_mask & upc); in qat_hal_set_pc()
777 static void qat_hal_get_uwords(struct icp_qat_fw_loader_handle *handle, in qat_hal_get_uwords() argument
784 qat_hal_rd_ae_csr(handle, ae, AE_MISC_CONTROL, &misc_control); in qat_hal_get_uwords()
785 qat_hal_wr_ae_csr(handle, ae, AE_MISC_CONTROL, in qat_hal_get_uwords()
787 qat_hal_rd_ae_csr(handle, ae, USTORE_ADDRESS, &ustore_addr); in qat_hal_get_uwords()
790 qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, uaddr); in qat_hal_get_uwords()
792 qat_hal_rd_ae_csr(handle, ae, USTORE_DATA_LOWER, &uwrd_lo); in qat_hal_get_uwords()
793 qat_hal_rd_ae_csr(handle, ae, USTORE_DATA_UPPER, &uwrd_hi); in qat_hal_get_uwords()
797 qat_hal_wr_ae_csr(handle, ae, AE_MISC_CONTROL, misc_control); in qat_hal_get_uwords()
798 qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, ustore_addr); in qat_hal_get_uwords()
801 void qat_hal_wr_umem(struct icp_qat_fw_loader_handle *handle, in qat_hal_wr_umem() argument
807 qat_hal_rd_ae_csr(handle, ae, USTORE_ADDRESS, &ustore_addr); in qat_hal_wr_umem()
809 qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, uaddr); in qat_hal_wr_umem()
820 qat_hal_wr_ae_csr(handle, ae, USTORE_DATA_LOWER, uwrd_lo); in qat_hal_wr_umem()
821 qat_hal_wr_ae_csr(handle, ae, USTORE_DATA_UPPER, uwrd_hi); in qat_hal_wr_umem()
823 qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, ustore_addr); in qat_hal_wr_umem()
827 static int qat_hal_exec_micro_inst(struct icp_qat_fw_loader_handle *handle, in qat_hal_exec_micro_inst() argument
843 if ((inst_num > handle->hal_handle->max_ustore) || !micro_inst) { in qat_hal_exec_micro_inst()
848 qat_hal_rd_indr_csr(handle, ae, ctx, LM_ADDR_0_INDIRECT, &ind_lm_addr0); in qat_hal_exec_micro_inst()
849 qat_hal_rd_indr_csr(handle, ae, ctx, LM_ADDR_1_INDIRECT, &ind_lm_addr1); in qat_hal_exec_micro_inst()
850 qat_hal_rd_indr_csr(handle, ae, ctx, INDIRECT_LM_ADDR_0_BYTE_INDEX, in qat_hal_exec_micro_inst()
852 qat_hal_rd_indr_csr(handle, ae, ctx, INDIRECT_LM_ADDR_1_BYTE_INDEX, in qat_hal_exec_micro_inst()
855 qat_hal_get_uwords(handle, ae, 0, inst_num, savuwords); in qat_hal_exec_micro_inst()
856 qat_hal_get_wakeup_event(handle, ae, ctx, &wakeup_events); in qat_hal_exec_micro_inst()
857 qat_hal_rd_indr_csr(handle, ae, ctx, CTX_STS_INDIRECT, &savpc); in qat_hal_exec_micro_inst()
858 savpc = (savpc & handle->hal_handle->upc_mask) >> 0; in qat_hal_exec_micro_inst()
859 qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx_enables); in qat_hal_exec_micro_inst()
861 qat_hal_rd_ae_csr(handle, ae, CC_ENABLE, &savcc); in qat_hal_exec_micro_inst()
862 qat_hal_rd_ae_csr(handle, ae, ACTIVE_CTX_STATUS, &savctx); in qat_hal_exec_micro_inst()
863 qat_hal_rd_ae_csr(handle, ae, CTX_ARB_CNTL, &ctxarb_ctl); in qat_hal_exec_micro_inst()
864 qat_hal_rd_indr_csr(handle, ae, ctx, FUTURE_COUNT_SIGNAL_INDIRECT, in qat_hal_exec_micro_inst()
866 qat_hal_rd_indr_csr(handle, ae, ctx, CTX_SIG_EVENTS_INDIRECT, &ind_sig); in qat_hal_exec_micro_inst()
867 qat_hal_rd_ae_csr(handle, ae, CTX_SIG_EVENTS_ACTIVE, &act_sig); in qat_hal_exec_micro_inst()
869 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables); in qat_hal_exec_micro_inst()
870 qat_hal_wr_uwords(handle, ae, 0, inst_num, micro_inst); in qat_hal_exec_micro_inst()
871 qat_hal_wr_indr_csr(handle, ae, (1 << ctx), CTX_STS_INDIRECT, 0); in qat_hal_exec_micro_inst()
872 qat_hal_wr_ae_csr(handle, ae, ACTIVE_CTX_STATUS, ctx & ACS_ACNO); in qat_hal_exec_micro_inst()
874 qat_hal_wr_ae_csr(handle, ae, CC_ENABLE, savcc & 0xffffdfff); in qat_hal_exec_micro_inst()
875 qat_hal_put_wakeup_event(handle, ae, (1 << ctx), XCWE_VOLUNTARY); in qat_hal_exec_micro_inst()
876 qat_hal_wr_indr_csr(handle, ae, (1 << ctx), CTX_SIG_EVENTS_INDIRECT, 0); in qat_hal_exec_micro_inst()
877 qat_hal_wr_ae_csr(handle, ae, CTX_SIG_EVENTS_ACTIVE, 0); in qat_hal_exec_micro_inst()
878 qat_hal_enable_ctx(handle, ae, (1 << ctx)); in qat_hal_exec_micro_inst()
880 if (qat_hal_wait_cycles(handle, ae, max_cycle, 1) != 0) in qat_hal_exec_micro_inst()
885 qat_hal_rd_indr_csr(handle, ae, ctx, CTX_STS_INDIRECT, in qat_hal_exec_micro_inst()
887 *endpc = ctx_status & handle->hal_handle->upc_mask; in qat_hal_exec_micro_inst()
890 qat_hal_disable_ctx(handle, ae, (1 << ctx)); in qat_hal_exec_micro_inst()
892 qat_hal_wr_uwords(handle, ae, 0, inst_num, savuwords); in qat_hal_exec_micro_inst()
893 qat_hal_put_wakeup_event(handle, ae, (1 << ctx), wakeup_events); in qat_hal_exec_micro_inst()
894 qat_hal_wr_indr_csr(handle, ae, (1 << ctx), CTX_STS_INDIRECT, in qat_hal_exec_micro_inst()
895 handle->hal_handle->upc_mask & savpc); in qat_hal_exec_micro_inst()
896 qat_hal_rd_ae_csr(handle, ae, AE_MISC_CONTROL, &csr_val); in qat_hal_exec_micro_inst()
898 qat_hal_wr_ae_csr(handle, ae, AE_MISC_CONTROL, newcsr_val); in qat_hal_exec_micro_inst()
899 qat_hal_wr_ae_csr(handle, ae, CC_ENABLE, savcc); in qat_hal_exec_micro_inst()
900 qat_hal_wr_ae_csr(handle, ae, ACTIVE_CTX_STATUS, savctx & ACS_ACNO); in qat_hal_exec_micro_inst()
901 qat_hal_wr_ae_csr(handle, ae, CTX_ARB_CNTL, ctxarb_ctl); in qat_hal_exec_micro_inst()
902 qat_hal_wr_indr_csr(handle, ae, (1 << ctx), in qat_hal_exec_micro_inst()
904 qat_hal_wr_indr_csr(handle, ae, (1 << ctx), in qat_hal_exec_micro_inst()
906 qat_hal_wr_indr_csr(handle, ae, (1 << ctx), in qat_hal_exec_micro_inst()
908 qat_hal_wr_indr_csr(handle, ae, (1 << ctx), in qat_hal_exec_micro_inst()
910 qat_hal_wr_indr_csr(handle, ae, (1 << ctx), in qat_hal_exec_micro_inst()
912 qat_hal_wr_indr_csr(handle, ae, (1 << ctx), in qat_hal_exec_micro_inst()
914 qat_hal_wr_ae_csr(handle, ae, CTX_SIG_EVENTS_ACTIVE, act_sig); in qat_hal_exec_micro_inst()
915 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables); in qat_hal_exec_micro_inst()
920 static int qat_hal_rd_rel_reg(struct icp_qat_fw_loader_handle *handle, in qat_hal_rd_rel_reg() argument
944 qat_hal_rd_ae_csr(handle, ae, ACTIVE_CTX_STATUS, &savctx); in qat_hal_rd_rel_reg()
945 qat_hal_rd_ae_csr(handle, ae, CTX_ARB_CNTL, &ctxarb_cntl); in qat_hal_rd_rel_reg()
946 qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx_enables); in qat_hal_rd_rel_reg()
949 qat_hal_wr_ae_csr(handle, ae, ACTIVE_CTX_STATUS, in qat_hal_rd_rel_reg()
951 qat_hal_get_uwords(handle, ae, 0, 1, &savuword); in qat_hal_rd_rel_reg()
952 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables); in qat_hal_rd_rel_reg()
953 qat_hal_rd_ae_csr(handle, ae, USTORE_ADDRESS, &ustore_addr); in qat_hal_rd_rel_reg()
955 qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, uaddr); in qat_hal_rd_rel_reg()
959 qat_hal_wr_ae_csr(handle, ae, USTORE_DATA_LOWER, uwrd_lo); in qat_hal_rd_rel_reg()
960 qat_hal_wr_ae_csr(handle, ae, USTORE_DATA_UPPER, uwrd_hi); in qat_hal_rd_rel_reg()
961 qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, uaddr); in qat_hal_rd_rel_reg()
963 qat_hal_wait_cycles(handle, ae, 0x8, 0); in qat_hal_rd_rel_reg()
969 qat_hal_rd_ae_csr(handle, ae, ALU_OUT, data); in qat_hal_rd_rel_reg()
970 qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, ustore_addr); in qat_hal_rd_rel_reg()
971 qat_hal_wr_uwords(handle, ae, 0, 1, &savuword); in qat_hal_rd_rel_reg()
973 qat_hal_wr_ae_csr(handle, ae, ACTIVE_CTX_STATUS, in qat_hal_rd_rel_reg()
975 qat_hal_wr_ae_csr(handle, ae, CTX_ARB_CNTL, ctxarb_cntl); in qat_hal_rd_rel_reg()
976 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables); in qat_hal_rd_rel_reg()
981 static int qat_hal_wr_rel_reg(struct icp_qat_fw_loader_handle *handle, in qat_hal_wr_rel_reg() argument
1024 return qat_hal_exec_micro_inst(handle, ae, ctx, insts, num_inst, in qat_hal_wr_rel_reg()
1062 static int qat_hal_exec_micro_init_lm(struct icp_qat_fw_loader_handle *handle, in qat_hal_exec_micro_init_lm() argument
1072 qat_hal_rd_rel_reg(handle, ae, ctx, ICP_GPA_REL, 0, &gpra0); in qat_hal_exec_micro_init_lm()
1073 qat_hal_rd_rel_reg(handle, ae, ctx, ICP_GPA_REL, 0x1, &gpra1); in qat_hal_exec_micro_init_lm()
1074 qat_hal_rd_rel_reg(handle, ae, ctx, ICP_GPA_REL, 0x2, &gpra2); in qat_hal_exec_micro_init_lm()
1075 qat_hal_rd_rel_reg(handle, ae, ctx, ICP_GPB_REL, 0, &gprb0); in qat_hal_exec_micro_init_lm()
1076 qat_hal_rd_rel_reg(handle, ae, ctx, ICP_GPB_REL, 0x1, &gprb1); in qat_hal_exec_micro_init_lm()
1079 stat = qat_hal_exec_micro_inst(handle, ae, ctx, micro_inst, inst_num, 1, in qat_hal_exec_micro_init_lm()
1083 qat_hal_wr_rel_reg(handle, ae, ctx, ICP_GPA_REL, 0, gpra0); in qat_hal_exec_micro_init_lm()
1084 qat_hal_wr_rel_reg(handle, ae, ctx, ICP_GPA_REL, 0x1, gpra1); in qat_hal_exec_micro_init_lm()
1085 qat_hal_wr_rel_reg(handle, ae, ctx, ICP_GPA_REL, 0x2, gpra2); in qat_hal_exec_micro_init_lm()
1086 qat_hal_wr_rel_reg(handle, ae, ctx, ICP_GPB_REL, 0, gprb0); in qat_hal_exec_micro_init_lm()
1087 qat_hal_wr_rel_reg(handle, ae, ctx, ICP_GPB_REL, 0x1, gprb1); in qat_hal_exec_micro_init_lm()
1092 int qat_hal_batch_wr_lm(struct icp_qat_fw_loader_handle *handle, in qat_hal_batch_wr_lm() argument
1105 if ((unsigned int)alloc_inst_size > handle->hal_handle->max_ustore) in qat_hal_batch_wr_lm()
1106 alloc_inst_size = handle->hal_handle->max_ustore; in qat_hal_batch_wr_lm()
1127 stat = qat_hal_exec_micro_init_lm(handle, ae, 0, &first_exec, in qat_hal_batch_wr_lm()
1135 static int qat_hal_put_rel_rd_xfer(struct icp_qat_fw_loader_handle *handle, in qat_hal_put_rel_rd_xfer() argument
1146 status = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx_enables); in qat_hal_put_rel_rd_xfer()
1163 SET_AE_XFER(handle, ae, reg_addr, val); in qat_hal_put_rel_rd_xfer()
1167 SET_AE_XFER(handle, ae, (reg_addr + dr_offset), val); in qat_hal_put_rel_rd_xfer()
1176 static int qat_hal_put_rel_wr_xfer(struct icp_qat_fw_loader_handle *handle, in qat_hal_put_rel_wr_xfer() argument
1196 qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx_enables); in qat_hal_put_rel_wr_xfer()
1213 qat_hal_rd_rel_reg(handle, ae, ctx, ICP_GPB_REL, gprnum, &gprval); in qat_hal_put_rel_wr_xfer()
1227 status = qat_hal_exec_micro_inst(handle, ae, ctx, micro_inst, num_inst, in qat_hal_put_rel_wr_xfer()
1229 qat_hal_wr_rel_reg(handle, ae, ctx, ICP_GPB_REL, gprnum, gprval); in qat_hal_put_rel_wr_xfer()
1233 static int qat_hal_put_rel_nn(struct icp_qat_fw_loader_handle *handle, in qat_hal_put_rel_nn() argument
1240 qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx_enables); in qat_hal_put_rel_nn()
1242 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables | CE_NN_MODE); in qat_hal_put_rel_nn()
1244 stat = qat_hal_put_rel_wr_xfer(handle, ae, ctx, ICP_NEIGH_REL, nn, val); in qat_hal_put_rel_nn()
1245 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables); in qat_hal_put_rel_nn()
1250 *handle, unsigned char ae, in qat_hal_convert_abs_to_rel()
1257 qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx_enables); in qat_hal_convert_abs_to_rel()
1270 int qat_hal_init_gpr(struct icp_qat_fw_loader_handle *handle, in qat_hal_init_gpr() argument
1285 qat_hal_convert_abs_to_rel(handle, ae, reg_num, ®, in qat_hal_init_gpr()
1294 stat = qat_hal_wr_rel_reg(handle, ae, ctx, type, reg, regdata); in qat_hal_init_gpr()
1304 int qat_hal_init_wr_xfer(struct icp_qat_fw_loader_handle *handle, in qat_hal_init_wr_xfer() argument
1319 qat_hal_convert_abs_to_rel(handle, ae, reg_num, ®, in qat_hal_init_wr_xfer()
1328 stat = qat_hal_put_rel_wr_xfer(handle, ae, ctx, type, reg, in qat_hal_init_wr_xfer()
1339 int qat_hal_init_rd_xfer(struct icp_qat_fw_loader_handle *handle, in qat_hal_init_rd_xfer() argument
1354 qat_hal_convert_abs_to_rel(handle, ae, reg_num, ®, in qat_hal_init_rd_xfer()
1363 stat = qat_hal_put_rel_rd_xfer(handle, ae, ctx, type, reg, in qat_hal_init_rd_xfer()
1374 int qat_hal_init_nn(struct icp_qat_fw_loader_handle *handle, in qat_hal_init_nn() argument
1387 stat = qat_hal_put_rel_nn(handle, ae, ctx, reg_num, regdata); in qat_hal_init_nn()