841 	unsigned int ctxarb_ctl, ctx_enables;  in qat_hal_exec_micro_inst()  local
859 	qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx_enables);  in qat_hal_exec_micro_inst()
860 	ctx_enables &= IGNORE_W1C_MASK;  in qat_hal_exec_micro_inst()
869 	qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables);  in qat_hal_exec_micro_inst()
915 	qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables);  in qat_hal_exec_micro_inst()
926 	unsigned int ctxarb_cntl, ustore_addr, ctx_enables;  in qat_hal_rd_rel_reg()  local
946 	qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx_enables);  in qat_hal_rd_rel_reg()
947 	ctx_enables &= IGNORE_W1C_MASK;  in qat_hal_rd_rel_reg()
952 	qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables);  in qat_hal_rd_rel_reg()
976 	qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables);  in qat_hal_rd_rel_reg()
1142 	unsigned int ctx_enables;  in qat_hal_put_rel_rd_xfer()  local
1146 	status = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx_enables);  in qat_hal_put_rel_rd_xfer()
1147 	if (CE_INUSE_CONTEXTS & ctx_enables) {  in qat_hal_put_rel_rd_xfer()
1181 	unsigned int gprval, ctx_enables;  in qat_hal_put_rel_wr_xfer()  local
1196 	qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx_enables);  in qat_hal_put_rel_wr_xfer()
1197 	if (CE_INUSE_CONTEXTS & ctx_enables) {  in qat_hal_put_rel_wr_xfer()
1237 	unsigned int ctx_enables;  in qat_hal_put_rel_nn()  local
1240 	qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx_enables);  in qat_hal_put_rel_nn()
1241 	ctx_enables &= IGNORE_W1C_MASK;  in qat_hal_put_rel_nn()
1242 	qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables | CE_NN_MODE);  in qat_hal_put_rel_nn()
1245 	qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables);  in qat_hal_put_rel_nn()
1255 	unsigned int ctx_enables;  in qat_hal_convert_abs_to_rel()  local
1257 	qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx_enables);  in qat_hal_convert_abs_to_rel()
1258 	if (ctx_enables & CE_INUSE_CONTEXTS) {  in qat_hal_convert_abs_to_rel()