Lines Matching refs:ctx
151 unsigned char ae, unsigned char ctx, in qat_hal_get_wakeup_event() argument
157 qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, ctx); in qat_hal_get_wakeup_event()
328 unsigned int ctx, cur_ctx; in qat_hal_wr_indr_csr() local
332 for (ctx = 0; ctx < ICP_QAT_UCLO_MAX_CTX; ctx++) { in qat_hal_wr_indr_csr()
333 if (!(ctx_mask & (1 << ctx))) in qat_hal_wr_indr_csr()
335 qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, ctx); in qat_hal_wr_indr_csr()
343 unsigned char ae, unsigned char ctx, in qat_hal_rd_indr_csr() argument
349 qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, ctx); in qat_hal_rd_indr_csr()
358 unsigned int ctx, cur_ctx; in qat_hal_put_sig_event() local
361 for (ctx = 0; ctx < ICP_QAT_UCLO_MAX_CTX; ctx++) { in qat_hal_put_sig_event()
362 if (!(ctx_mask & (1 << ctx))) in qat_hal_put_sig_event()
364 qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, ctx); in qat_hal_put_sig_event()
374 unsigned int ctx, cur_ctx; in qat_hal_put_wakeup_event() local
377 for (ctx = 0; ctx < ICP_QAT_UCLO_MAX_CTX; ctx++) { in qat_hal_put_wakeup_event()
378 if (!(ctx_mask & (1 << ctx))) in qat_hal_put_wakeup_event()
380 qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, ctx); in qat_hal_put_wakeup_event()
528 unsigned int ctx; in qat_hal_disable_ctx() local
530 qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx); in qat_hal_disable_ctx()
531 ctx &= IGNORE_W1C_MASK & in qat_hal_disable_ctx()
533 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx); in qat_hal_disable_ctx()
592 unsigned int ctx; in qat_hal_enable_ctx() local
594 qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES, &ctx); in qat_hal_enable_ctx()
595 ctx &= IGNORE_W1C_MASK; in qat_hal_enable_ctx()
596 ctx_mask &= (ctx & CE_INUSE_CONTEXTS) ? 0x55 : 0xFF; in qat_hal_enable_ctx()
597 ctx |= (ctx_mask << CE_ENABLE_BITPOS); in qat_hal_enable_ctx()
598 qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx); in qat_hal_enable_ctx()
828 unsigned char ae, unsigned char ctx, in qat_hal_exec_micro_inst() argument
848 qat_hal_rd_indr_csr(handle, ae, ctx, LM_ADDR_0_INDIRECT, &ind_lm_addr0); in qat_hal_exec_micro_inst()
849 qat_hal_rd_indr_csr(handle, ae, ctx, LM_ADDR_1_INDIRECT, &ind_lm_addr1); in qat_hal_exec_micro_inst()
850 qat_hal_rd_indr_csr(handle, ae, ctx, INDIRECT_LM_ADDR_0_BYTE_INDEX, in qat_hal_exec_micro_inst()
852 qat_hal_rd_indr_csr(handle, ae, ctx, INDIRECT_LM_ADDR_1_BYTE_INDEX, in qat_hal_exec_micro_inst()
856 qat_hal_get_wakeup_event(handle, ae, ctx, &wakeup_events); in qat_hal_exec_micro_inst()
857 qat_hal_rd_indr_csr(handle, ae, ctx, CTX_STS_INDIRECT, &savpc); in qat_hal_exec_micro_inst()
864 qat_hal_rd_indr_csr(handle, ae, ctx, FUTURE_COUNT_SIGNAL_INDIRECT, in qat_hal_exec_micro_inst()
866 qat_hal_rd_indr_csr(handle, ae, ctx, CTX_SIG_EVENTS_INDIRECT, &ind_sig); in qat_hal_exec_micro_inst()
871 qat_hal_wr_indr_csr(handle, ae, (1 << ctx), CTX_STS_INDIRECT, 0); in qat_hal_exec_micro_inst()
872 qat_hal_wr_ae_csr(handle, ae, ACTIVE_CTX_STATUS, ctx & ACS_ACNO); in qat_hal_exec_micro_inst()
875 qat_hal_put_wakeup_event(handle, ae, (1 << ctx), XCWE_VOLUNTARY); in qat_hal_exec_micro_inst()
876 qat_hal_wr_indr_csr(handle, ae, (1 << ctx), CTX_SIG_EVENTS_INDIRECT, 0); in qat_hal_exec_micro_inst()
878 qat_hal_enable_ctx(handle, ae, (1 << ctx)); in qat_hal_exec_micro_inst()
885 qat_hal_rd_indr_csr(handle, ae, ctx, CTX_STS_INDIRECT, in qat_hal_exec_micro_inst()
890 qat_hal_disable_ctx(handle, ae, (1 << ctx)); in qat_hal_exec_micro_inst()
893 qat_hal_put_wakeup_event(handle, ae, (1 << ctx), wakeup_events); in qat_hal_exec_micro_inst()
894 qat_hal_wr_indr_csr(handle, ae, (1 << ctx), CTX_STS_INDIRECT, in qat_hal_exec_micro_inst()
902 qat_hal_wr_indr_csr(handle, ae, (1 << ctx), in qat_hal_exec_micro_inst()
904 qat_hal_wr_indr_csr(handle, ae, (1 << ctx), in qat_hal_exec_micro_inst()
906 qat_hal_wr_indr_csr(handle, ae, (1 << ctx), in qat_hal_exec_micro_inst()
908 qat_hal_wr_indr_csr(handle, ae, (1 << ctx), in qat_hal_exec_micro_inst()
910 qat_hal_wr_indr_csr(handle, ae, (1 << ctx), in qat_hal_exec_micro_inst()
912 qat_hal_wr_indr_csr(handle, ae, (1 << ctx), in qat_hal_exec_micro_inst()
921 unsigned char ae, unsigned char ctx, in qat_hal_rd_rel_reg() argument
948 if (ctx != (savctx & ACS_ACNO)) in qat_hal_rd_rel_reg()
950 ctx & ACS_ACNO); in qat_hal_rd_rel_reg()
972 if (ctx != (savctx & ACS_ACNO)) in qat_hal_rd_rel_reg()
982 unsigned char ae, unsigned char ctx, in qat_hal_wr_rel_reg() argument
1024 return qat_hal_exec_micro_inst(handle, ae, ctx, insts, num_inst, in qat_hal_wr_rel_reg()
1063 unsigned char ae, unsigned char ctx, in qat_hal_exec_micro_init_lm() argument
1072 qat_hal_rd_rel_reg(handle, ae, ctx, ICP_GPA_REL, 0, &gpra0); in qat_hal_exec_micro_init_lm()
1073 qat_hal_rd_rel_reg(handle, ae, ctx, ICP_GPA_REL, 0x1, &gpra1); in qat_hal_exec_micro_init_lm()
1074 qat_hal_rd_rel_reg(handle, ae, ctx, ICP_GPA_REL, 0x2, &gpra2); in qat_hal_exec_micro_init_lm()
1075 qat_hal_rd_rel_reg(handle, ae, ctx, ICP_GPB_REL, 0, &gprb0); in qat_hal_exec_micro_init_lm()
1076 qat_hal_rd_rel_reg(handle, ae, ctx, ICP_GPB_REL, 0x1, &gprb1); in qat_hal_exec_micro_init_lm()
1079 stat = qat_hal_exec_micro_inst(handle, ae, ctx, micro_inst, inst_num, 1, in qat_hal_exec_micro_init_lm()
1083 qat_hal_wr_rel_reg(handle, ae, ctx, ICP_GPA_REL, 0, gpra0); in qat_hal_exec_micro_init_lm()
1084 qat_hal_wr_rel_reg(handle, ae, ctx, ICP_GPA_REL, 0x1, gpra1); in qat_hal_exec_micro_init_lm()
1085 qat_hal_wr_rel_reg(handle, ae, ctx, ICP_GPA_REL, 0x2, gpra2); in qat_hal_exec_micro_init_lm()
1086 qat_hal_wr_rel_reg(handle, ae, ctx, ICP_GPB_REL, 0, gprb0); in qat_hal_exec_micro_init_lm()
1087 qat_hal_wr_rel_reg(handle, ae, ctx, ICP_GPB_REL, 0x1, gprb1); in qat_hal_exec_micro_init_lm()
1136 unsigned char ae, unsigned char ctx, in qat_hal_put_rel_rd_xfer() argument
1148 if (ctx & 0x1) { in qat_hal_put_rel_rd_xfer()
1149 pr_err("QAT: bad 4-ctx mode,ctx=0x%x\n", ctx); in qat_hal_put_rel_rd_xfer()
1159 reg_addr = reg_num + (ctx << 0x5); in qat_hal_put_rel_rd_xfer()
1177 unsigned char ae, unsigned char ctx, in qat_hal_put_rel_wr_xfer() argument
1198 if (ctx & 0x1) { in qat_hal_put_rel_wr_xfer()
1199 pr_err("QAT: 4-ctx mode,ctx=0x%x\n", ctx); in qat_hal_put_rel_wr_xfer()
1213 qat_hal_rd_rel_reg(handle, ae, ctx, ICP_GPB_REL, gprnum, &gprval); in qat_hal_put_rel_wr_xfer()
1227 status = qat_hal_exec_micro_inst(handle, ae, ctx, micro_inst, num_inst, in qat_hal_put_rel_wr_xfer()
1229 qat_hal_wr_rel_reg(handle, ae, ctx, ICP_GPB_REL, gprnum, gprval); in qat_hal_put_rel_wr_xfer()
1234 unsigned char ae, unsigned char ctx, in qat_hal_put_rel_nn() argument
1244 stat = qat_hal_put_rel_wr_xfer(handle, ae, ctx, ICP_NEIGH_REL, nn, val); in qat_hal_put_rel_nn()
1253 unsigned char *ctx) in qat_hal_convert_abs_to_rel() argument
1261 *ctx = (absreg_num >> 0x4) & 0x6; in qat_hal_convert_abs_to_rel()
1265 *ctx = (absreg_num >> 0x4) & 0x7; in qat_hal_convert_abs_to_rel()
1277 unsigned char ctx = 0; in qat_hal_init_gpr() local
1286 &ctx); in qat_hal_init_gpr()
1291 if (!test_bit(ctx, (unsigned long *)&ctx_mask)) in qat_hal_init_gpr()
1294 stat = qat_hal_wr_rel_reg(handle, ae, ctx, type, reg, regdata); in qat_hal_init_gpr()
1299 } while (ctx_mask && (ctx++ < ICP_QAT_UCLO_MAX_CTX)); in qat_hal_init_gpr()
1311 unsigned char ctx = 0; in qat_hal_init_wr_xfer() local
1320 &ctx); in qat_hal_init_wr_xfer()
1325 if (!test_bit(ctx, (unsigned long *)&ctx_mask)) in qat_hal_init_wr_xfer()
1328 stat = qat_hal_put_rel_wr_xfer(handle, ae, ctx, type, reg, in qat_hal_init_wr_xfer()
1334 } while (ctx_mask && (ctx++ < ICP_QAT_UCLO_MAX_CTX)); in qat_hal_init_wr_xfer()
1346 unsigned char ctx = 0; in qat_hal_init_rd_xfer() local
1355 &ctx); in qat_hal_init_rd_xfer()
1360 if (!test_bit(ctx, (unsigned long *)&ctx_mask)) in qat_hal_init_rd_xfer()
1363 stat = qat_hal_put_rel_rd_xfer(handle, ae, ctx, type, reg, in qat_hal_init_rd_xfer()
1369 } while (ctx_mask && (ctx++ < ICP_QAT_UCLO_MAX_CTX)); in qat_hal_init_rd_xfer()
1379 unsigned char ctx; in qat_hal_init_nn() local
1384 for (ctx = 0; ctx < ICP_QAT_UCLO_MAX_CTX; ctx++) { in qat_hal_init_nn()
1385 if (!test_bit(ctx, (unsigned long *)&ctx_mask)) in qat_hal_init_nn()
1387 stat = qat_hal_put_rel_nn(handle, ae, ctx, reg_num, regdata); in qat_hal_init_nn()