102 #define SET_CAP_CSR(handle, csr, val) \  argument
103 	ADF_CSR_WR(handle->hal_cap_g_ctl_csr_addr_v, csr, val)
104 #define GET_CAP_CSR(handle, csr) \  argument
105 	ADF_CSR_RD(handle->hal_cap_g_ctl_csr_addr_v, csr)
106 #define SET_GLB_CSR(handle, csr, val) SET_CAP_CSR(handle, csr + GLOBAL_CSR, val)  argument
107 #define GET_GLB_CSR(handle, csr) GET_CAP_CSR(handle, GLOBAL_CSR + csr)  argument
108 #define AE_CSR(handle, ae) \  argument
109 	(handle->hal_cap_ae_local_csr_addr_v + \
110 	((ae & handle->hal_handle->ae_mask) << 12))
111 #define AE_CSR_ADDR(handle, ae, csr) (AE_CSR(handle, ae) + (0x3ff & csr))  argument
112 #define SET_AE_CSR(handle, ae, csr, val) \  argument
113 	ADF_CSR_WR(AE_CSR_ADDR(handle, ae, csr), 0, val)
114 #define GET_AE_CSR(handle, ae, csr) ADF_CSR_RD(AE_CSR_ADDR(handle, ae, csr), 0)  argument
115 #define AE_XFER(handle, ae) \  argument
116 	(handle->hal_cap_ae_xfer_csr_addr_v + \
117 	((ae & handle->hal_handle->ae_mask) << 12))
118 #define AE_XFER_ADDR(handle, ae, reg) (AE_XFER(handle, ae) + \  argument
120 #define SET_AE_XFER(handle, ae, reg, val) \  argument
121 	ADF_CSR_WR(AE_XFER_ADDR(handle, ae, reg), 0, val)
122 #define SRAM_WRITE(handle, addr, val) \  argument
123 	ADF_CSR_WR(handle->hal_sram_addr_v, addr, val)
124 #define SRAM_READ(handle, addr) ADF_CSR_RD(handle->hal_sram_addr_v, addr)  argument