Lines Matching refs:HIFN_1_DMA_CSR
194 #define HIFN_1_DMA_CSR 0x40 /* DMA Status and Control */ macro
716 hifn_write_1(dev, HIFN_1_DMA_CSR, in hifn_stop_device()
1045 hifn_write_1(dev, HIFN_1_DMA_CSR, in hifn_init_registers()
1059 hifn_write_1(dev, HIFN_1_DMA_CSR, in hifn_init_registers()
1073 hifn_read_1(dev, HIFN_1_DMA_CSR); in hifn_init_registers()
1272 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_C_CTRL_ENA); in hifn_setup_cmd_desc()
1307 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_S_CTRL_ENA); in hifn_setup_src_desc()
1334 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_R_CTRL_ENA); in hifn_setup_res_desc()
1363 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_D_CTRL_ENA); in hifn_setup_dst_desc()
1910 hifn_write_1(dev, HIFN_1_DMA_CSR, r); in hifn_work()
1958 dmacsr = hifn_read_1(dev, HIFN_1_DMA_CSR); in hifn_interrupt()
1969 hifn_write_1(dev, HIFN_1_DMA_CSR, dmacsr & dev->dmareg); in hifn_interrupt()
1987 hifn_write_1(dev, HIFN_1_DMA_CSR, dmacsr & (HIFN_DMACSR_R_OVER | in hifn_interrupt()