Lines Matching refs:u32
130 #define REG64_MS32(reg) ((u32 __iomem *)(reg))
131 #define REG64_LS32(reg) ((u32 __iomem *)(reg) + 1)
133 #define REG64_MS32(reg) ((u32 __iomem *)(reg) + 1)
134 #define REG64_LS32(reg) ((u32 __iomem *)(reg))
156 u32 jrstatus; /* Status for completed descriptor */
235 u32 cha_rev_ms; /* CRNR - CHA Rev No. Most significant half*/
236 u32 cha_rev_ls; /* CRNR - CHA Rev No. Least significant half*/
243 u32 comp_parms_ms; /* CTPR - Compile Parameters Register */
244 u32 comp_parms_ls; /* CTPR - Compile Parameters Register */
249 u32 faultliodn; /* FALR - Fault Address LIODN */
250 u32 faultdetail; /* FADR - Fault Addr Detail */
251 u32 rsvd2;
252 u32 status; /* CSTA - CAAM Status */
256 u32 rtic_id; /* RVID - RTIC Version ID */
257 u32 ccb_id; /* CCBVID - CCB Version ID */
258 u32 cha_id_ms; /* CHAVID - CHA Version ID Most Significant*/
259 u32 cha_id_ls; /* CHAVID - CHA Version ID Least Significant*/
260 u32 cha_num_ms; /* CHANUM - CHA Number Most Significant */
261 u32 cha_num_ls; /* CHANUM - CHA Number Least Significant*/
262 u32 caam_id_ms; /* CAAMVID - CAAM Version ID MS */
263 u32 caam_id_ls; /* CAAMVID - CAAM Version ID LS */
272 u32 liodn_ms; /* lock and make-trusted control bits */
273 u32 liodn_ls; /* LIODN for non-sequence and seq access */
278 u32 rsvd1;
279 u32 pidr; /* partition ID, DECO */
285 u32 mode; /* RTSTMODEx - Test mode */
286 u32 rsvd1[3];
287 u32 reset; /* RTSTRESETx - Test reset control */
288 u32 rsvd2[3];
289 u32 status; /* RTSTSSTATUSx - Test status */
290 u32 rsvd3;
291 u32 errstat; /* RTSTERRSTATx - Test error status */
292 u32 rsvd4;
293 u32 errctl; /* RTSTERRCTLx - Test error control */
294 u32 rsvd5;
295 u32 entropy; /* RTSTENTROPYx - Test entropy */
296 u32 rsvd6[15];
297 u32 verifctl; /* RTSTVERIFCTLx - Test verification control */
298 u32 rsvd7;
299 u32 verifstat; /* RTSTVERIFSTATx - Test verification status */
300 u32 rsvd8;
301 u32 verifdata; /* RTSTVERIFDx - Test verification data */
302 u32 rsvd9;
303 u32 xkey; /* RTSTXKEYx - Test XKEY */
304 u32 rsvd10;
305 u32 oscctctl; /* RTSTOSCCTCTLx - Test osc. counter control */
306 u32 rsvd11;
307 u32 oscct; /* RTSTOSCCTx - Test oscillator counter */
308 u32 rsvd12;
309 u32 oscctstat; /* RTSTODCCTSTATx - Test osc counter status */
310 u32 rsvd13[2];
311 u32 ofifo[4]; /* RTSTOFIFOx - Test output FIFO */
312 u32 rsvd14[15];
328 u32 rtmctl; /* misc. control register */
329 u32 rtscmisc; /* statistical check misc. register */
330 u32 rtpkrrng; /* poker range register */
332 u32 rtpkrmax; /* PRGM=1: poker max. limit register */
333 u32 rtpkrsq; /* PRGM=0: poker square calc. result register */
339 u32 rtsdctl; /* seed control register */
341 u32 rtsblim; /* PRGM=1: sparse bit limit register */
342 u32 rttotsam; /* PRGM=0: total samples register */
344 u32 rtfrqmin; /* frequency count min. limit register */
347 u32 rtfrqmax; /* PRGM=1: freq. count max. limit register */
348 u32 rtfrqcnt; /* PRGM=0: freq. count register */
350 u32 rsvd1[40];
356 u32 rdsta;
357 u32 rsvd2[15];
379 u32 rsvd1;
380 u32 mcr; /* MCFG Master Config Register */
381 u32 rsvd2;
382 u32 scfgr; /* SCFGR, Security Config Register */
387 u32 rsvd3[11];
388 u32 jrstart; /* JRSTART - Job Ring Start Register */
390 u32 rsvd4[5];
391 u32 deco_rsr; /* DECORSR - Deco Request Source */
392 u32 rsvd11;
393 u32 deco_rq; /* DECORR - DECO Request */
395 u32 rsvd5[22];
398 u32 deco_avail; /* DAR - DECO availability */
399 u32 deco_reset; /* DRR - DECO reset */
400 u32 rsvd6[182];
404 u32 kek[KEK_KEY_SIZE]; /* JDKEKR - Key Encryption Key */
405 u32 tkek[TKEK_KEY_SIZE]; /* TDKEKR - Trusted Desc KEK */
406 u32 tdsk[TDSK_KEY_SIZE]; /* TDSKR - Trusted Desc Signing Key */
407 u32 rsvd7[32];
409 u32 rsvd8[70];
418 u32 rsvd9[448];
474 u32 rsvd1;
475 u32 inpring_size; /* IRSx - Input ring size */
476 u32 rsvd2;
477 u32 inpring_avail; /* IRSAx - Input ring room remaining */
478 u32 rsvd3;
479 u32 inpring_jobadd; /* IRJAx - Input ring jobs added */
483 u32 rsvd4;
484 u32 outring_size; /* ORSx - Output ring size */
485 u32 rsvd5;
486 u32 outring_rmvd; /* ORJRx - Output ring jobs removed */
487 u32 rsvd6;
488 u32 outring_used; /* ORSFx - Output ring slots full */
491 u32 rsvd7;
492 u32 jroutstatus; /* JRSTAx - JobR output status */
493 u32 rsvd8;
494 u32 jrintstatus; /* JRINTx - JobR interrupt status */
495 u32 rconfig_hi; /* JRxCFG - Ring configuration */
496 u32 rconfig_lo;
499 u32 rsvd9;
500 u32 inp_rdidx; /* IRRIx - Input ring read index */
501 u32 rsvd10;
502 u32 out_wtidx; /* ORWIx - Output ring write index */
505 u32 rsvd11;
506 u32 jrcommand; /* JRCRx - JobR command */
508 u32 rsvd12[932];
638 u32 rsvd;
639 u32 length;
647 u32 memhash_be[32];
648 u32 memhash_le[32];
653 u32 rsvd1;
654 u32 status; /* RSTA - Status */
655 u32 rsvd2;
656 u32 cmd; /* RCMD - Command */
657 u32 rsvd3;
658 u32 ctrl; /* RCTL - Control */
659 u32 rsvd4;
660 u32 throttle; /* RTHR - Throttle */
661 u32 rsvd5[2];
663 u32 rsvd6;
664 u32 rend; /* REND - Endian corrections */
665 u32 rsvd7[50];
669 u32 rsvd8[32];
673 u32 rsvd_3[640];
682 u32 qi_control_hi; /* QICTL - QI Control */
683 u32 qi_control_lo;
684 u32 rsvd1;
685 u32 qi_status; /* QISTA - QI Status */
686 u32 qi_deq_cfg_hi; /* QIDQC - QI Dequeue Configuration */
687 u32 qi_deq_cfg_lo;
688 u32 qi_enq_cfg_hi; /* QISEQC - QI Enqueue Command */
689 u32 qi_enq_cfg_lo;
690 u32 rsvd2[1016];
730 u32 elen; /* E, F bits + 30-bit length */
731 u32 bpid_offset; /* Buffer Pool ID + 16-bit length */
744 u32 rsvd1;
745 u32 cls1_mode; /* CxC1MR - Class 1 Mode */
746 u32 rsvd2;
747 u32 cls1_keysize; /* CxC1KSR - Class 1 Key Size */
748 u32 cls1_datasize_hi; /* CxC1DSR - Class 1 Data Size */
749 u32 cls1_datasize_lo;
750 u32 rsvd3;
751 u32 cls1_icvsize; /* CxC1ICVSR - Class 1 ICV size */
752 u32 rsvd4[5];
753 u32 cha_ctrl; /* CCTLR - CHA control */
754 u32 rsvd5;
755 u32 irq_crtl; /* CxCIRQ - CCB interrupt done/error/clear */
756 u32 rsvd6;
757 u32 clr_written; /* CxCWR - Clear-Written */
758 u32 ccb_status_hi; /* CxCSTA - CCB Status/Error */
759 u32 ccb_status_lo;
760 u32 rsvd7[3];
761 u32 aad_size; /* CxAADSZR - Current AAD Size */
762 u32 rsvd8;
763 u32 cls1_iv_size; /* CxC1IVSZR - Current Class 1 IV Size */
764 u32 rsvd9[7];
765 u32 pkha_a_size; /* PKASZRx - Size of PKHA A */
766 u32 rsvd10;
767 u32 pkha_b_size; /* PKBSZRx - Size of PKHA B */
768 u32 rsvd11;
769 u32 pkha_n_size; /* PKNSZRx - Size of PKHA N */
770 u32 rsvd12;
771 u32 pkha_e_size; /* PKESZRx - Size of PKHA E */
772 u32 rsvd13[24];
773 u32 cls1_ctx[16]; /* CxC1CTXR - Class 1 Context @100 */
774 u32 rsvd14[48];
775 u32 cls1_key[8]; /* CxC1KEYR - Class 1 Key @200 */
776 u32 rsvd15[121];
777 u32 cls2_mode; /* CxC2MR - Class 2 Mode */
778 u32 rsvd16;
779 u32 cls2_keysize; /* CxX2KSR - Class 2 Key Size */
780 u32 cls2_datasize_hi; /* CxC2DSR - Class 2 Data Size */
781 u32 cls2_datasize_lo;
782 u32 rsvd17;
783 u32 cls2_icvsize; /* CxC2ICVSZR - Class 2 ICV Size */
784 u32 rsvd18[56];
785 u32 cls2_ctx[18]; /* CxC2CTXR - Class 2 Context @500 */
786 u32 rsvd19[46];
787 u32 cls2_key[32]; /* CxC2KEYR - Class2 Key @600 */
788 u32 rsvd20[84];
789 u32 inp_infofifo_hi; /* CxIFIFO - Input Info FIFO @7d0 */
790 u32 inp_infofifo_lo;
791 u32 rsvd21[2];
793 u32 rsvd22[2];
795 u32 rsvd23[2];
796 u32 jr_ctl_hi; /* CxJRR - JobR Control Register @800 */
797 u32 jr_ctl_lo;
800 u32 op_status_hi; /* DxOPSTA - DECO Operation Status */
801 u32 op_status_lo;
802 u32 rsvd24[2];
803 u32 liodn; /* DxLSR - DECO LIODN Status - non-seq */
804 u32 td_liodn; /* DxLSR - DECO LIODN Status - trustdesc */
805 u32 rsvd26[6];
807 u32 rsvd27[8];
809 u32 rsvd28[16];
811 u32 rsvd29[48];
812 u32 descbuf[64]; /* DxDESB - Descriptor buffer */
813 u32 rscvd30[193];
817 u32 desc_dbg; /* DxDDR - DECO Debug Register */
818 u32 rsvd31[126];