Lines Matching defs:caam_deco
743 struct caam_deco { struct
744 u32 rsvd1;
745 u32 cls1_mode; /* CxC1MR - Class 1 Mode */
746 u32 rsvd2;
747 u32 cls1_keysize; /* CxC1KSR - Class 1 Key Size */
748 u32 cls1_datasize_hi; /* CxC1DSR - Class 1 Data Size */
749 u32 cls1_datasize_lo;
750 u32 rsvd3;
751 u32 cls1_icvsize; /* CxC1ICVSR - Class 1 ICV size */
752 u32 rsvd4[5];
753 u32 cha_ctrl; /* CCTLR - CHA control */
754 u32 rsvd5;
755 u32 irq_crtl; /* CxCIRQ - CCB interrupt done/error/clear */
756 u32 rsvd6;
757 u32 clr_written; /* CxCWR - Clear-Written */
758 u32 ccb_status_hi; /* CxCSTA - CCB Status/Error */
759 u32 ccb_status_lo;
760 u32 rsvd7[3];
761 u32 aad_size; /* CxAADSZR - Current AAD Size */
762 u32 rsvd8;
763 u32 cls1_iv_size; /* CxC1IVSZR - Current Class 1 IV Size */
764 u32 rsvd9[7];
765 u32 pkha_a_size; /* PKASZRx - Size of PKHA A */
766 u32 rsvd10;
767 u32 pkha_b_size; /* PKBSZRx - Size of PKHA B */
768 u32 rsvd11;
769 u32 pkha_n_size; /* PKNSZRx - Size of PKHA N */
770 u32 rsvd12;
771 u32 pkha_e_size; /* PKESZRx - Size of PKHA E */
772 u32 rsvd13[24];
773 u32 cls1_ctx[16]; /* CxC1CTXR - Class 1 Context @100 */
774 u32 rsvd14[48];
775 u32 cls1_key[8]; /* CxC1KEYR - Class 1 Key @200 */
776 u32 rsvd15[121];
777 u32 cls2_mode; /* CxC2MR - Class 2 Mode */
778 u32 rsvd16;
779 u32 cls2_keysize; /* CxX2KSR - Class 2 Key Size */
780 u32 cls2_datasize_hi; /* CxC2DSR - Class 2 Data Size */
781 u32 cls2_datasize_lo;
782 u32 rsvd17;
783 u32 cls2_icvsize; /* CxC2ICVSZR - Class 2 ICV Size */
784 u32 rsvd18[56];
785 u32 cls2_ctx[18]; /* CxC2CTXR - Class 2 Context @500 */
786 u32 rsvd19[46];
787 u32 cls2_key[32]; /* CxC2KEYR - Class2 Key @600 */
788 u32 rsvd20[84];
789 u32 inp_infofifo_hi; /* CxIFIFO - Input Info FIFO @7d0 */
790 u32 inp_infofifo_lo;
791 u32 rsvd21[2];
792 u64 inp_datafifo; /* CxDFIFO - Input Data FIFO */
793 u32 rsvd22[2];
794 u64 out_datafifo; /* CxOFIFO - Output Data FIFO */
795 u32 rsvd23[2];
796 u32 jr_ctl_hi; /* CxJRR - JobR Control Register @800 */
797 u32 jr_ctl_lo;
798 u64 jr_descaddr; /* CxDADR - JobR Descriptor Address */
800 u32 op_status_hi; /* DxOPSTA - DECO Operation Status */
801 u32 op_status_lo;
802 u32 rsvd24[2];
803 u32 liodn; /* DxLSR - DECO LIODN Status - non-seq */
804 u32 td_liodn; /* DxLSR - DECO LIODN Status - trustdesc */
805 u32 rsvd26[6];
806 u64 math[4]; /* DxMTH - Math register */
807 u32 rsvd27[8];
808 struct deco_sg_table gthr_tbl[4]; /* DxGTR - Gather Tables */
809 u32 rsvd28[16];
810 struct deco_sg_table sctr_tbl[4]; /* DxSTR - Scatter Tables */
811 u32 rsvd29[48];
812 u32 descbuf[64]; /* DxDESB - Descriptor buffer */
813 u32 rscvd30[193];
817 u32 desc_dbg; /* DxDDR - DECO Debug Register */
818 u32 rsvd31[126];