Lines Matching refs:cmd
273 struct drv_cmd *cmd = _cmd; in do_drv_read() local
276 switch (cmd->type) { in do_drv_read()
279 rdmsr(cmd->addr.msr.reg, cmd->val, h); in do_drv_read()
282 acpi_os_read_port((acpi_io_address)cmd->addr.io.port, in do_drv_read()
283 &cmd->val, in do_drv_read()
284 (u32)cmd->addr.io.bit_width); in do_drv_read()
294 struct drv_cmd *cmd = _cmd; in do_drv_write() local
297 switch (cmd->type) { in do_drv_write()
299 rdmsr(cmd->addr.msr.reg, lo, hi); in do_drv_write()
300 lo = (lo & ~INTEL_MSR_RANGE) | (cmd->val & INTEL_MSR_RANGE); in do_drv_write()
301 wrmsr(cmd->addr.msr.reg, lo, hi); in do_drv_write()
304 wrmsr(cmd->addr.msr.reg, cmd->val, 0); in do_drv_write()
307 acpi_os_write_port((acpi_io_address)cmd->addr.io.port, in do_drv_write()
308 cmd->val, in do_drv_write()
309 (u32)cmd->addr.io.bit_width); in do_drv_write()
316 static void drv_read(struct drv_cmd *cmd) in drv_read() argument
319 cmd->val = 0; in drv_read()
321 err = smp_call_function_any(cmd->mask, do_drv_read, cmd, 1); in drv_read()
325 static void drv_write(struct drv_cmd *cmd) in drv_write() argument
330 if (cpumask_test_cpu(this_cpu, cmd->mask)) in drv_write()
331 do_drv_write(cmd); in drv_write()
332 smp_call_function_many(cmd->mask, do_drv_write, cmd, 1); in drv_write()
340 struct drv_cmd cmd; in get_cur_val() local
347 cmd.type = SYSTEM_INTEL_MSR_CAPABLE; in get_cur_val()
348 cmd.addr.msr.reg = MSR_IA32_PERF_CTL; in get_cur_val()
351 cmd.type = SYSTEM_AMD_MSR_CAPABLE; in get_cur_val()
352 cmd.addr.msr.reg = MSR_AMD_PERF_CTL; in get_cur_val()
355 cmd.type = SYSTEM_IO_CAPABLE; in get_cur_val()
357 cmd.addr.io.port = perf->control_register.address; in get_cur_val()
358 cmd.addr.io.bit_width = perf->control_register.bit_width; in get_cur_val()
364 cmd.mask = mask; in get_cur_val()
365 drv_read(&cmd); in get_cur_val()
367 pr_debug("get_cur_val = %u\n", cmd.val); in get_cur_val()
369 return cmd.val; in get_cur_val()
424 struct drv_cmd cmd; in acpi_cpufreq_target() local
448 cmd.type = SYSTEM_INTEL_MSR_CAPABLE; in acpi_cpufreq_target()
449 cmd.addr.msr.reg = MSR_IA32_PERF_CTL; in acpi_cpufreq_target()
450 cmd.val = (u32) perf->states[next_perf_state].control; in acpi_cpufreq_target()
453 cmd.type = SYSTEM_AMD_MSR_CAPABLE; in acpi_cpufreq_target()
454 cmd.addr.msr.reg = MSR_AMD_PERF_CTL; in acpi_cpufreq_target()
455 cmd.val = (u32) perf->states[next_perf_state].control; in acpi_cpufreq_target()
458 cmd.type = SYSTEM_IO_CAPABLE; in acpi_cpufreq_target()
459 cmd.addr.io.port = perf->control_register.address; in acpi_cpufreq_target()
460 cmd.addr.io.bit_width = perf->control_register.bit_width; in acpi_cpufreq_target()
461 cmd.val = (u32) perf->states[next_perf_state].control; in acpi_cpufreq_target()
470 cmd.mask = policy->cpus; in acpi_cpufreq_target()
472 cmd.mask = cpumask_of(policy->cpu); in acpi_cpufreq_target()
474 drv_write(&cmd); in acpi_cpufreq_target()
477 if (!check_freqs(cmd.mask, data->freq_table[index].frequency, in acpi_cpufreq_target()