Lines Matching refs:writel_relaxed
49 writel_relaxed(0, base + TIM_CR1); in stm32_clock_event_shutdown()
59 writel_relaxed(data->periodic_top, base + TIM_ARR); in stm32_clock_event_set_periodic()
60 writel_relaxed(TIM_CR1_ARPE | TIM_CR1_CEN, base + TIM_CR1); in stm32_clock_event_set_periodic()
70 writel_relaxed(evt, data->base + TIM_ARR); in stm32_clock_event_set_next_event()
71 writel_relaxed(TIM_CR1_ARPE | TIM_CR1_OPM | TIM_CR1_CEN, in stm32_clock_event_set_next_event()
81 writel_relaxed(0, data->base + TIM_SR); in stm32_clock_event_handler()
144 writel_relaxed(~0U, data->base + TIM_ARR); in stm32_clockevent_init()
153 writel_relaxed(0, data->base + TIM_ARR); in stm32_clockevent_init()
155 writel_relaxed(prescaler - 1, data->base + TIM_PSC); in stm32_clockevent_init()
156 writel_relaxed(TIM_EGR_UG, data->base + TIM_EGR); in stm32_clockevent_init()
157 writel_relaxed(TIM_DIER_UIE, data->base + TIM_DIER); in stm32_clockevent_init()
158 writel_relaxed(0, data->base + TIM_SR); in stm32_clockevent_init()