Lines Matching refs:ATMEL_TC_REG
51 upper = __raw_readl(tcaddr + ATMEL_TC_REG(1, CV)); in tc_get_cycles()
52 lower = __raw_readl(tcaddr + ATMEL_TC_REG(0, CV)); in tc_get_cycles()
53 } while (upper != __raw_readl(tcaddr + ATMEL_TC_REG(1, CV))); in tc_get_cycles()
61 return __raw_readl(tcaddr + ATMEL_TC_REG(0, CV)); in tc_get_cycles32()
99 __raw_writel(0xff, regs + ATMEL_TC_REG(2, IDR)); in tc_shutdown()
100 __raw_writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR)); in tc_shutdown()
119 ATMEL_TC_WAVESEL_UP_AUTO, regs + ATMEL_TC_REG(2, CMR)); in tc_set_oneshot()
120 __raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER)); in tc_set_oneshot()
141 regs + ATMEL_TC_REG(2, CMR)); in tc_set_periodic()
142 __raw_writel((32768 + HZ / 2) / HZ, tcaddr + ATMEL_TC_REG(2, RC)); in tc_set_periodic()
145 __raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER)); in tc_set_periodic()
149 ATMEL_TC_REG(2, CCR)); in tc_set_periodic()
155 __raw_writel(delta, tcaddr + ATMEL_TC_REG(2, RC)); in tc_next_event()
159 tcaddr + ATMEL_TC_REG(2, CCR)); in tc_next_event()
182 sr = __raw_readl(dev->regs + ATMEL_TC_REG(2, SR)); in ch2_irq()
247 tcaddr + ATMEL_TC_REG(0, CMR)); in tcb_setup_dual_chan()
248 __raw_writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA)); in tcb_setup_dual_chan()
249 __raw_writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC)); in tcb_setup_dual_chan()
250 __raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR)); /* no irqs */ in tcb_setup_dual_chan()
251 __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR)); in tcb_setup_dual_chan()
257 tcaddr + ATMEL_TC_REG(1, CMR)); in tcb_setup_dual_chan()
258 __raw_writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR)); /* no irqs */ in tcb_setup_dual_chan()
259 __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR)); in tcb_setup_dual_chan()
273 tcaddr + ATMEL_TC_REG(0, CMR)); in tcb_setup_single_chan()
274 __raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR)); /* no irqs */ in tcb_setup_single_chan()
275 __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR)); in tcb_setup_single_chan()