58 static void __iomem *base;  variable
63 	writel(TIMER1_DISABLE, base + TIMER_CR);  in moxart_shutdown()
69 	writel(TIMER1_DISABLE, base + TIMER_CR);  in moxart_set_oneshot()
70 	writel(~0, base + TIMER1_BASE + REG_LOAD);  in moxart_set_oneshot()
76 	writel(clock_count_per_tick, base + TIMER1_BASE + REG_LOAD);  in moxart_set_periodic()
77 	writel(TIMER1_ENABLE, base + TIMER_CR);  in moxart_set_periodic()
86 	writel(TIMER1_DISABLE, base + TIMER_CR);  in moxart_clkevt_next_event()
88 	u = readl(base + TIMER1_BASE + REG_COUNT) - cycles;  in moxart_clkevt_next_event()
89 	writel(u, base + TIMER1_BASE + REG_MATCH1);  in moxart_clkevt_next_event()
91 	writel(TIMER1_ENABLE, base + TIMER_CR);  in moxart_clkevt_next_event()
128 	base = of_iomap(node, 0);  in moxart_timer_init()
129 	if (!base)  in moxart_timer_init()
146 	if (clocksource_mmio_init(base + TIMER2_BASE + REG_COUNT,  in moxart_timer_init()
153 	writel(~0, base + TIMER2_BASE + REG_LOAD);  in moxart_timer_init()
154 	writel(TIMEREG_CR_2_ENABLE, base + TIMER_CR);  in moxart_timer_init()