44 static inline unsigned long read_tcnt32(struct tpu_priv *p)  in read_tcnt32()  argument
48 	tcnt = ctrl_inw(p->mapbase1 + TCNT) << 16;  in read_tcnt32()
49 	tcnt |= ctrl_inw(p->mapbase2 + TCNT);  in read_tcnt32()
53 static int tpu_get_counter(struct tpu_priv *p, unsigned long long *val)  in tpu_get_counter()  argument
58 	o1 = ctrl_inb(p->mapbase1 + TSR) & 0x10;  in tpu_get_counter()
63 		v1 = read_tcnt32(p);  in tpu_get_counter()
64 		v2 = read_tcnt32(p);  in tpu_get_counter()
65 		v3 = read_tcnt32(p);  in tpu_get_counter()
66 		o1 = ctrl_inb(p->mapbase1 + TSR) & 0x10;  in tpu_get_counter()
81 	struct tpu_priv *p = cs_to_priv(cs);  in tpu_clocksource_read()  local
85 	raw_spin_lock_irqsave(&p->lock, flags);  in tpu_clocksource_read()
86 	if (tpu_get_counter(p, &value))  in tpu_clocksource_read()
88 	raw_spin_unlock_irqrestore(&p->lock, flags);  in tpu_clocksource_read()
95 	struct tpu_priv *p = cs_to_priv(cs);  in tpu_clocksource_enable()  local
97 	WARN_ON(p->cs_enabled);  in tpu_clocksource_enable()
99 	ctrl_outw(0, p->mapbase1 + TCNT);  in tpu_clocksource_enable()
100 	ctrl_outw(0, p->mapbase2 + TCNT);  in tpu_clocksource_enable()
101 	ctrl_outb(0x0f, p->mapbase1 + TCR);  in tpu_clocksource_enable()
102 	ctrl_outb(0x03, p->mapbase2 + TCR);  in tpu_clocksource_enable()
104 	p->cs_enabled = true;  in tpu_clocksource_enable()
110 	struct tpu_priv *p = cs_to_priv(cs);  in tpu_clocksource_disable()  local
112 	WARN_ON(!p->cs_enabled);  in tpu_clocksource_disable()
114 	ctrl_outb(0, p->mapbase1 + TCR);  in tpu_clocksource_disable()
115 	ctrl_outb(0, p->mapbase2 + TCR);  in tpu_clocksource_disable()
116 	p->cs_enabled = false;  in tpu_clocksource_disable()
122 static int __init tpu_setup(struct tpu_priv *p, struct platform_device *pdev)  in tpu_setup()  argument
126 	p->pdev = pdev;  in tpu_setup()
128 	res[CH_L] = platform_get_resource(p->pdev, IORESOURCE_MEM, CH_L);  in tpu_setup()
129 	res[CH_H] = platform_get_resource(p->pdev, IORESOURCE_MEM, CH_H);  in tpu_setup()
131 		dev_err(&p->pdev->dev, "failed to get I/O memory\n");  in tpu_setup()
135 	p->clk = clk_get(&p->pdev->dev, "fck");  in tpu_setup()
136 	if (IS_ERR(p->clk)) {  in tpu_setup()
137 		dev_err(&p->pdev->dev, "can't get clk\n");  in tpu_setup()
138 		return PTR_ERR(p->clk);  in tpu_setup()
141 	p->mapbase1 = res[CH_L]->start;  in tpu_setup()
142 	p->mapbase2 = res[CH_H]->start;  in tpu_setup()
144 	p->cs.name = pdev->name;  in tpu_setup()
145 	p->cs.rating = 200;  in tpu_setup()
146 	p->cs.read = tpu_clocksource_read;  in tpu_setup()
147 	p->cs.enable = tpu_clocksource_enable;  in tpu_setup()
148 	p->cs.disable = tpu_clocksource_disable;  in tpu_setup()
149 	p->cs.mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8);  in tpu_setup()
150 	p->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;  in tpu_setup()
151 	clocksource_register_hz(&p->cs, clk_get_rate(p->clk) / 64);  in tpu_setup()
152 	platform_set_drvdata(pdev, p);  in tpu_setup()
159 	struct tpu_priv *p = platform_get_drvdata(pdev);  in tpu_probe()  local
161 	if (p) {  in tpu_probe()
166 	p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);  in tpu_probe()
167 	if (!p)  in tpu_probe()
170 	return tpu_setup(p, pdev);  in tpu_probe()