Lines Matching refs:ddata
32 } ddata; variable
36 writel_relaxed(0, ddata.base + LPC_LPT_START_OFF); in st_clksrc_reset()
37 writel_relaxed(0, ddata.base + LPC_LPT_MSB_OFF); in st_clksrc_reset()
38 writel_relaxed(0, ddata.base + LPC_LPT_LSB_OFF); in st_clksrc_reset()
39 writel_relaxed(1, ddata.base + LPC_LPT_START_OFF); in st_clksrc_reset()
44 return (u64)readl_relaxed(ddata.base + LPC_LPT_LSB_OFF); in st_clksrc_sched_clock_read()
54 rate = clk_get_rate(ddata.clk); in st_clksrc_init()
58 ret = clocksource_mmio_init(ddata.base + LPC_LPT_LSB_OFF, in st_clksrc_init()
90 ddata.clk = clk; in st_clksrc_setup_clk()
110 ddata.base = of_iomap(np, 0); in st_clksrc_of_register()
111 if (!ddata.base) { in st_clksrc_of_register()
117 iounmap(ddata.base); in st_clksrc_of_register()
122 clk_disable_unprepare(ddata.clk); in st_clksrc_of_register()
123 clk_put(ddata.clk); in st_clksrc_of_register()
124 iounmap(ddata.base); in st_clksrc_of_register()
129 clk_get_rate(ddata.clk)); in st_clksrc_of_register()
131 CLOCKSOURCE_OF_DECLARE(ddata, "st,stih407-lpc", st_clksrc_of_register);