145 	clk = clk_register_mux(NULL, mux_name, parents, 4,  in zynq_clk_register_fclk()
149 	clk = clk_register_divider(NULL, div0_name, mux_name,  in zynq_clk_register_fclk()
153 	clk = clk_register_divider(NULL, div1_name, div0_name,  in zynq_clk_register_fclk()
158 	clks[fclk] = clk_register_gate(NULL, clk_name,  in zynq_clk_register_fclk()
203 	clk = clk_register_mux(NULL, mux_name, parents, 4,  in zynq_clk_register_periph_clk()
206 	clk = clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6,  in zynq_clk_register_periph_clk()
209 	clks[clk0] = clk_register_gate(NULL, clk_name0, div_name,  in zynq_clk_register_periph_clk()
212 		clks[clk1] = clk_register_gate(NULL, clk_name1, div_name,  in zynq_clk_register_periph_clk()
268 	ps_clk = clk_register_fixed_rate(NULL, "ps_clk", NULL, CLK_IS_ROOT,  in zynq_clk_setup()
274 	clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll],  in zynq_clk_setup()
280 	clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll],  in zynq_clk_setup()
286 	clks[iopll] = clk_register_mux(NULL, clk_output_name[iopll],  in zynq_clk_setup()
292 	clk = clk_register_mux(NULL, "cpu_mux", cpu_parents, 4,  in zynq_clk_setup()
295 	clk = clk_register_divider(NULL, "cpu_div", "cpu_mux", 0,  in zynq_clk_setup()
299 	clks[cpu_6or4x] = clk_register_gate(NULL, clk_output_name[cpu_6or4x],  in zynq_clk_setup()
303 	clk = clk_register_fixed_factor(NULL, "cpu_3or2x_div", "cpu_div", 0,  in zynq_clk_setup()
305 	clks[cpu_3or2x] = clk_register_gate(NULL, clk_output_name[cpu_3or2x],  in zynq_clk_setup()
309 	clk = clk_register_fixed_factor(NULL, "cpu_2x_div", "cpu_div", 0, 1,  in zynq_clk_setup()
311 	clks[cpu_2x] = clk_register_gate(NULL, clk_output_name[cpu_2x],  in zynq_clk_setup()
316 	clk = clk_register_fixed_factor(NULL, "cpu_1x_div", "cpu_div", 0, 1,  in zynq_clk_setup()
318 	clks[cpu_1x] = clk_register_gate(NULL, clk_output_name[cpu_1x],  in zynq_clk_setup()
333 	clks[swdt] = clk_register_mux(NULL, clk_output_name[swdt],  in zynq_clk_setup()
339 	clk = clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0,  in zynq_clk_setup()
342 	clks[ddr2x] = clk_register_gate(NULL, clk_output_name[ddr2x],  in zynq_clk_setup()
345 	clk = clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0,  in zynq_clk_setup()
348 	clks[ddr3x] = clk_register_gate(NULL, clk_output_name[ddr3x],  in zynq_clk_setup()
352 	clk = clk_register_divider(NULL, "dci_div0", "ddrpll", 0,  in zynq_clk_setup()
355 	clk = clk_register_divider(NULL, "dci_div1", "dci_div0",  in zynq_clk_setup()
359 	clks[dci] = clk_register_gate(NULL, clk_output_name[dci], "dci_div1",  in zynq_clk_setup()
372 	zynq_clk_register_periph_clk(lqspi, 0, clk_output_name[lqspi], NULL,  in zynq_clk_setup()
375 	zynq_clk_register_periph_clk(smc, 0, clk_output_name[smc], NULL,  in zynq_clk_setup()
378 	zynq_clk_register_periph_clk(pcap, 0, clk_output_name[pcap], NULL,  in zynq_clk_setup()
400 	clk = clk_register_mux(NULL, "gem0_mux", periph_parents, 4,  in zynq_clk_setup()
403 	clk = clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0,  in zynq_clk_setup()
406 	clk = clk_register_divider(NULL, "gem0_div1", "gem0_div0",  in zynq_clk_setup()
410 	clk = clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2,  in zynq_clk_setup()
414 	clks[gem0] = clk_register_gate(NULL, clk_output_name[gem0],  in zynq_clk_setup()
425 	clk = clk_register_mux(NULL, "gem1_mux", periph_parents, 4,  in zynq_clk_setup()
428 	clk = clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0,  in zynq_clk_setup()
431 	clk = clk_register_divider(NULL, "gem1_div1", "gem1_div0",  in zynq_clk_setup()
435 	clk = clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2,  in zynq_clk_setup()
439 	clks[gem1] = clk_register_gate(NULL, clk_output_name[gem1],  in zynq_clk_setup()
457 	clk = clk_register_mux(NULL, "can_mux", periph_parents, 4,  in zynq_clk_setup()
460 	clk = clk_register_divider(NULL, "can_div0", "can_mux", 0,  in zynq_clk_setup()
463 	clk = clk_register_divider(NULL, "can_div1", "can_div0",  in zynq_clk_setup()
467 	clk = clk_register_gate(NULL, "can0_gate", "can_div1",  in zynq_clk_setup()
470 	clk = clk_register_gate(NULL, "can1_gate", "can_div1",  in zynq_clk_setup()
473 	clk = clk_register_mux(NULL, "can0_mio_mux",  in zynq_clk_setup()
477 	clk = clk_register_mux(NULL, "can1_mio_mux",  in zynq_clk_setup()
481 	clks[can0] = clk_register_mux(NULL, clk_output_name[can0],  in zynq_clk_setup()
485 	clks[can1] = clk_register_mux(NULL, clk_output_name[can1],  in zynq_clk_setup()
497 	clk = clk_register_mux(NULL, "dbg_mux", periph_parents, 4,  in zynq_clk_setup()
500 	clk = clk_register_divider(NULL, "dbg_div", "dbg_mux", 0,  in zynq_clk_setup()
503 	clk = clk_register_mux(NULL, "dbg_emio_mux", dbg_emio_mux_parents, 2,  in zynq_clk_setup()
506 	clks[dbg_trc] = clk_register_gate(NULL, clk_output_name[dbg_trc],  in zynq_clk_setup()
509 	clks[dbg_apb] = clk_register_gate(NULL, clk_output_name[dbg_apb],  in zynq_clk_setup()
523 	clks[dma] = clk_register_gate(NULL, clk_output_name[dma],  in zynq_clk_setup()
526 	clks[usb0_aper] = clk_register_gate(NULL, clk_output_name[usb0_aper],  in zynq_clk_setup()
529 	clks[usb1_aper] = clk_register_gate(NULL, clk_output_name[usb1_aper],  in zynq_clk_setup()
532 	clks[gem0_aper] = clk_register_gate(NULL, clk_output_name[gem0_aper],  in zynq_clk_setup()
535 	clks[gem1_aper] = clk_register_gate(NULL, clk_output_name[gem1_aper],  in zynq_clk_setup()
538 	clks[sdio0_aper] = clk_register_gate(NULL, clk_output_name[sdio0_aper],  in zynq_clk_setup()
541 	clks[sdio1_aper] = clk_register_gate(NULL, clk_output_name[sdio1_aper],  in zynq_clk_setup()
544 	clks[spi0_aper] = clk_register_gate(NULL, clk_output_name[spi0_aper],  in zynq_clk_setup()
547 	clks[spi1_aper] = clk_register_gate(NULL, clk_output_name[spi1_aper],  in zynq_clk_setup()
550 	clks[can0_aper] = clk_register_gate(NULL, clk_output_name[can0_aper],  in zynq_clk_setup()
553 	clks[can1_aper] = clk_register_gate(NULL, clk_output_name[can1_aper],  in zynq_clk_setup()
556 	clks[i2c0_aper] = clk_register_gate(NULL, clk_output_name[i2c0_aper],  in zynq_clk_setup()
559 	clks[i2c1_aper] = clk_register_gate(NULL, clk_output_name[i2c1_aper],  in zynq_clk_setup()
562 	clks[uart0_aper] = clk_register_gate(NULL, clk_output_name[uart0_aper],  in zynq_clk_setup()
565 	clks[uart1_aper] = clk_register_gate(NULL, clk_output_name[uart1_aper],  in zynq_clk_setup()
568 	clks[gpio_aper] = clk_register_gate(NULL, clk_output_name[gpio_aper],  in zynq_clk_setup()
571 	clks[lqspi_aper] = clk_register_gate(NULL, clk_output_name[lqspi_aper],  in zynq_clk_setup()
574 	clks[smc_aper] = clk_register_gate(NULL, clk_output_name[smc_aper],  in zynq_clk_setup()
599 	np = of_find_compatible_node(NULL, NULL, "xlnx,ps7-clkc");  in zynq_clock_init()