Lines Matching refs:CLK_DIVIDER_ALLOW_ZERO
151 CLK_DIVIDER_ALLOW_ZERO, fclk_lock); in zynq_clk_register_fclk()
155 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in zynq_clk_register_fclk()
207 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock); in zynq_clk_register_periph_clk()
297 CLK_DIVIDER_ALLOW_ZERO, &armclk_lock); in zynq_clk_setup()
341 CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock); in zynq_clk_setup()
347 CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock); in zynq_clk_setup()
354 CLK_DIVIDER_ALLOW_ZERO, &dciclk_lock); in zynq_clk_setup()
357 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in zynq_clk_setup()
405 CLK_DIVIDER_ALLOW_ZERO, &gem0clk_lock); in zynq_clk_setup()
408 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in zynq_clk_setup()
430 CLK_DIVIDER_ALLOW_ZERO, &gem1clk_lock); in zynq_clk_setup()
433 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in zynq_clk_setup()
462 CLK_DIVIDER_ALLOW_ZERO, &canclk_lock); in zynq_clk_setup()
465 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in zynq_clk_setup()
502 CLK_DIVIDER_ALLOW_ZERO, &dbgclk_lock); in zynq_clk_setup()