116 				CLK_IS_ROOT|CLK_SET_RATE_GATE);  in u8540_clk_init()
125 				CLK_IS_ROOT|CLK_SET_RATE_GATE);  in u8540_clk_init()
128 				CLK_IS_ROOT|CLK_SET_RATE_GATE);  in u8540_clk_init()
131 				CLK_IS_ROOT|CLK_SET_RATE_GATE);  in u8540_clk_init()
167 				CLK_IS_ROOT|CLK_SET_RATE_GATE);  in u8540_clk_init()
186 					CLK_IS_ROOT|CLK_SET_RATE_GATE);  in u8540_clk_init()
191 					CLK_IS_ROOT|CLK_SET_RATE_GATE);  in u8540_clk_init()
201 				CLK_IS_ROOT|CLK_SET_RATE_GATE);  in u8540_clk_init()
205 				PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE);  in u8540_clk_init()
210 				PRCMU_PLLDSI_LCD, 0, CLK_SET_RATE_GATE);  in u8540_clk_init()
214 				PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE);  in u8540_clk_init()
218 				PRCMU_DSI0CLK_LCD, 0, CLK_SET_RATE_GATE);  in u8540_clk_init()
223 				PRCMU_DSI1CLK, 0, CLK_SET_RATE_GATE);  in u8540_clk_init()
227 				PRCMU_DSI1CLK_LCD, 0, CLK_SET_RATE_GATE);  in u8540_clk_init()
232 				PRCMU_DSI0ESCCLK, 0, CLK_SET_RATE_GATE);  in u8540_clk_init()
237 				PRCMU_DSI1ESCCLK, 0, CLK_SET_RATE_GATE);  in u8540_clk_init()
242 				PRCMU_DSI2ESCCLK, 0, CLK_SET_RATE_GATE);  in u8540_clk_init()
479 			bases[CLKRST1_INDEX], BIT(0), CLK_SET_RATE_GATE);  in u8540_clk_init()
483 			bases[CLKRST1_INDEX], BIT(1), CLK_SET_RATE_GATE);  in u8540_clk_init()
487 			bases[CLKRST1_INDEX], BIT(2), CLK_SET_RATE_GATE);  in u8540_clk_init()
491 			bases[CLKRST1_INDEX], BIT(3), CLK_SET_RATE_GATE);  in u8540_clk_init()
496 			bases[CLKRST1_INDEX], BIT(4), CLK_SET_RATE_GATE);  in u8540_clk_init()
501 			bases[CLKRST1_INDEX], BIT(5), CLK_SET_RATE_GATE);  in u8540_clk_init()
505 			bases[CLKRST1_INDEX], BIT(6), CLK_SET_RATE_GATE);  in u8540_clk_init()
509 			bases[CLKRST1_INDEX], BIT(8), CLK_SET_RATE_GATE);  in u8540_clk_init()
513 			bases[CLKRST1_INDEX], BIT(9), CLK_SET_RATE_GATE);  in u8540_clk_init()
517 			bases[CLKRST1_INDEX], BIT(10), CLK_SET_RATE_GATE);  in u8540_clk_init()
523 			bases[CLKRST2_INDEX], BIT(0), CLK_SET_RATE_GATE);  in u8540_clk_init()
527 			bases[CLKRST2_INDEX], BIT(1), CLK_SET_RATE_GATE);  in u8540_clk_init()
531 			bases[CLKRST2_INDEX], BIT(2), CLK_SET_RATE_GATE);  in u8540_clk_init()
535 			bases[CLKRST2_INDEX], BIT(3), CLK_SET_RATE_GATE);  in u8540_clk_init()
540 			bases[CLKRST2_INDEX], BIT(4), CLK_SET_RATE_GATE);  in u8540_clk_init()
544 			bases[CLKRST2_INDEX], BIT(5), CLK_SET_RATE_GATE);  in u8540_clk_init()
549 			CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);  in u8540_clk_init()
554 			CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);  in u8540_clk_init()
559 			bases[CLKRST2_INDEX], BIT(9), CLK_SET_RATE_GATE);  in u8540_clk_init()
565 			bases[CLKRST3_INDEX], BIT(1), CLK_SET_RATE_GATE);  in u8540_clk_init()
569 			bases[CLKRST3_INDEX], BIT(2), CLK_SET_RATE_GATE);  in u8540_clk_init()
573 			bases[CLKRST3_INDEX], BIT(3), CLK_SET_RATE_GATE);  in u8540_clk_init()
577 			bases[CLKRST3_INDEX], BIT(4), CLK_SET_RATE_GATE);  in u8540_clk_init()
581 			bases[CLKRST3_INDEX], BIT(5), CLK_SET_RATE_GATE);  in u8540_clk_init()
586 			bases[CLKRST3_INDEX], BIT(6), CLK_SET_RATE_GATE);  in u8540_clk_init()
590 			bases[CLKRST3_INDEX], BIT(7), CLK_SET_RATE_GATE);  in u8540_clk_init()
594 			bases[CLKRST3_INDEX], BIT(8), CLK_SET_RATE_GATE);  in u8540_clk_init()
598 			bases[CLKRST3_INDEX], BIT(9), CLK_SET_RATE_GATE);  in u8540_clk_init()
602 			bases[CLKRST3_INDEX], BIT(10), CLK_SET_RATE_GATE);  in u8540_clk_init()
606 			bases[CLKRST3_INDEX], BIT(11), CLK_SET_RATE_GATE);  in u8540_clk_init()
611 			bases[CLKRST6_INDEX], BIT(0), CLK_SET_RATE_GATE);  in u8540_clk_init()