Lines Matching refs:clk_hw

184 typedef void (*ti_of_clk_init_cb_t)(struct clk_hw *, struct device_node *);
193 struct clk_hw *ti_clk_build_component_div(struct ti_clk_divider *setup);
194 struct clk_hw *ti_clk_build_component_gate(struct ti_clk_gate *setup);
195 struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup);
203 int ti_clk_retry_init(struct device_node *node, struct clk_hw *hw,
205 int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type);
207 void omap2_init_clk_hw_omap_clocks(struct clk_hw *hw);
227 int omap2_clkops_enable_clkdm(struct clk_hw *hw);
228 void omap2_clkops_disable_clkdm(struct clk_hw *hw);
230 int omap2_dflt_clk_enable(struct clk_hw *hw);
231 void omap2_dflt_clk_disable(struct clk_hw *hw);
232 int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
243 u8 omap2_init_dpll_parent(struct clk_hw *hw);
244 int omap3_noncore_dpll_enable(struct clk_hw *hw);
245 void omap3_noncore_dpll_disable(struct clk_hw *hw);
246 int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index);
247 int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
249 int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,
253 int omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
255 long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
257 unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
260 unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
261 int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
263 int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
267 unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
269 long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
272 int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,