Lines Matching refs:writel_relaxed
999 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2); in tegra114_utmi_param_configure()
1017 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); in tegra114_utmi_param_configure()
1024 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra114_utmi_param_configure()
1029 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); in tegra114_utmi_param_configure()
1038 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra114_utmi_param_configure()
1045 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra114_utmi_param_configure()
1354 writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT); in tegra114_clock_tune_cpu_trimmers_high()
1381 writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT); in tegra114_clock_tune_cpu_trimmers_low()
1403 writel_relaxed(r, clk_base + CPU_FINETRIM_R); in tegra114_clock_tune_cpu_trimmers_init()
1412 writel_relaxed(dr, clk_base + CPU_FINETRIM_DR); in tegra114_clock_tune_cpu_trimmers_init()
1429 writel_relaxed(v, clk_base + RST_DFLL_DVCO); in tegra114_clock_assert_dfll_dvco_reset()
1446 writel_relaxed(v, clk_base + RST_DFLL_DVCO); in tegra114_clock_deassert_dfll_dvco_reset()