Lines Matching refs:con_id
864 { .con_id = "clk_m", .dt_id = TEGRA114_CLK_CLK_M },
865 { .con_id = "pll_ref", .dt_id = TEGRA114_CLK_PLL_REF },
866 { .con_id = "clk_32k", .dt_id = TEGRA114_CLK_CLK_32K },
867 { .con_id = "clk_m_div2", .dt_id = TEGRA114_CLK_CLK_M_DIV2 },
868 { .con_id = "clk_m_div4", .dt_id = TEGRA114_CLK_CLK_M_DIV4 },
869 { .con_id = "pll_c", .dt_id = TEGRA114_CLK_PLL_C },
870 { .con_id = "pll_c_out1", .dt_id = TEGRA114_CLK_PLL_C_OUT1 },
871 { .con_id = "pll_c2", .dt_id = TEGRA114_CLK_PLL_C2 },
872 { .con_id = "pll_c3", .dt_id = TEGRA114_CLK_PLL_C3 },
873 { .con_id = "pll_p", .dt_id = TEGRA114_CLK_PLL_P },
874 { .con_id = "pll_p_out1", .dt_id = TEGRA114_CLK_PLL_P_OUT1 },
875 { .con_id = "pll_p_out2", .dt_id = TEGRA114_CLK_PLL_P_OUT2 },
876 { .con_id = "pll_p_out3", .dt_id = TEGRA114_CLK_PLL_P_OUT3 },
877 { .con_id = "pll_p_out4", .dt_id = TEGRA114_CLK_PLL_P_OUT4 },
878 { .con_id = "pll_m", .dt_id = TEGRA114_CLK_PLL_M },
879 { .con_id = "pll_m_out1", .dt_id = TEGRA114_CLK_PLL_M_OUT1 },
880 { .con_id = "pll_x", .dt_id = TEGRA114_CLK_PLL_X },
881 { .con_id = "pll_x_out0", .dt_id = TEGRA114_CLK_PLL_X_OUT0 },
882 { .con_id = "pll_u", .dt_id = TEGRA114_CLK_PLL_U },
883 { .con_id = "pll_u_480M", .dt_id = TEGRA114_CLK_PLL_U_480M },
884 { .con_id = "pll_u_60M", .dt_id = TEGRA114_CLK_PLL_U_60M },
885 { .con_id = "pll_u_48M", .dt_id = TEGRA114_CLK_PLL_U_48M },
886 { .con_id = "pll_u_12M", .dt_id = TEGRA114_CLK_PLL_U_12M },
887 { .con_id = "pll_d", .dt_id = TEGRA114_CLK_PLL_D },
888 { .con_id = "pll_d_out0", .dt_id = TEGRA114_CLK_PLL_D_OUT0 },
889 { .con_id = "pll_d2", .dt_id = TEGRA114_CLK_PLL_D2 },
890 { .con_id = "pll_d2_out0", .dt_id = TEGRA114_CLK_PLL_D2_OUT0 },
891 { .con_id = "pll_a", .dt_id = TEGRA114_CLK_PLL_A },
892 { .con_id = "pll_a_out0", .dt_id = TEGRA114_CLK_PLL_A_OUT0 },
893 { .con_id = "pll_re_vco", .dt_id = TEGRA114_CLK_PLL_RE_VCO },
894 { .con_id = "pll_re_out", .dt_id = TEGRA114_CLK_PLL_RE_OUT },
895 { .con_id = "pll_e_out0", .dt_id = TEGRA114_CLK_PLL_E_OUT0 },
896 { .con_id = "spdif_in_sync", .dt_id = TEGRA114_CLK_SPDIF_IN_SYNC },
897 { .con_id = "i2s0_sync", .dt_id = TEGRA114_CLK_I2S0_SYNC },
898 { .con_id = "i2s1_sync", .dt_id = TEGRA114_CLK_I2S1_SYNC },
899 { .con_id = "i2s2_sync", .dt_id = TEGRA114_CLK_I2S2_SYNC },
900 { .con_id = "i2s3_sync", .dt_id = TEGRA114_CLK_I2S3_SYNC },
901 { .con_id = "i2s4_sync", .dt_id = TEGRA114_CLK_I2S4_SYNC },
902 { .con_id = "vimclk_sync", .dt_id = TEGRA114_CLK_VIMCLK_SYNC },
903 { .con_id = "audio0", .dt_id = TEGRA114_CLK_AUDIO0 },
904 { .con_id = "audio1", .dt_id = TEGRA114_CLK_AUDIO1 },
905 { .con_id = "audio2", .dt_id = TEGRA114_CLK_AUDIO2 },
906 { .con_id = "audio3", .dt_id = TEGRA114_CLK_AUDIO3 },
907 { .con_id = "audio4", .dt_id = TEGRA114_CLK_AUDIO4 },
908 { .con_id = "spdif", .dt_id = TEGRA114_CLK_SPDIF },
909 { .con_id = "audio0_2x", .dt_id = TEGRA114_CLK_AUDIO0_2X },
910 { .con_id = "audio1_2x", .dt_id = TEGRA114_CLK_AUDIO1_2X },
911 { .con_id = "audio2_2x", .dt_id = TEGRA114_CLK_AUDIO2_2X },
912 { .con_id = "audio3_2x", .dt_id = TEGRA114_CLK_AUDIO3_2X },
913 { .con_id = "audio4_2x", .dt_id = TEGRA114_CLK_AUDIO4_2X },
914 { .con_id = "spdif_2x", .dt_id = TEGRA114_CLK_SPDIF_2X },
915 { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA114_CLK_EXTERN1 },
916 { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA114_CLK_EXTERN2 },
917 { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA114_CLK_EXTERN3 },
918 { .con_id = "blink", .dt_id = TEGRA114_CLK_BLINK },
919 { .con_id = "cclk_g", .dt_id = TEGRA114_CLK_CCLK_G },
920 { .con_id = "cclk_lp", .dt_id = TEGRA114_CLK_CCLK_LP },
921 { .con_id = "sclk", .dt_id = TEGRA114_CLK_SCLK },
922 { .con_id = "hclk", .dt_id = TEGRA114_CLK_HCLK },
923 { .con_id = "pclk", .dt_id = TEGRA114_CLK_PCLK },
924 { .con_id = "fuse", .dt_id = TEGRA114_CLK_FUSE },