131 			    _clk_num, _gate_flags, _clk_id)	\  argument
134 			_clk_num,  _gate_flags, _clk_id, _parents##_idx, 0,\
138 			    _clk_num, _gate_flags, _clk_id, flags)\  argument
141 			_clk_num, _gate_flags, _clk_id, _parents##_idx, flags,\
145 			     _clk_num, _gate_flags, _clk_id)	\  argument
148 			_clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\
151 #define MUX8_NOGATE_LOCK(_name, _parents, _offset, _clk_id, _lock)	\  argument
154 			      0, TEGRA_PERIPH_NO_GATE, _clk_id,\
158 			    _clk_num, _gate_flags, _clk_id)	\  argument
162 			_clk_id, _parents##_idx, 0, NULL)
165 			    _clk_num, _gate_flags, _clk_id, flags)\  argument
169 			_clk_id, _parents##_idx, flags, NULL)
172 			    _clk_num, _gate_flags, _clk_id)	\  argument
176 			_clk_id, _parents##_idx, 0, NULL)
179 			     _clk_num, _clk_id)			\  argument
182 			TEGRA_DIVIDER_ROUND_UP, _clk_num, 0, _clk_id,\
186 			     _clk_num, _clk_id)			\  argument
189 			_clk_num, 0, _clk_id, _parents##_idx, 0, NULL)
192 			     _clk_num, _gate_flags, _clk_id)	 \  argument
196 			_clk_id, _parents##_idx, 0, NULL)
199 				 _gate_flags, _clk_id)		\  argument
203 			_clk_id, mux_d_audio_clk_idx, 0, NULL)
207 			      _gate_flags, _clk_id, _lock)		\  argument
211 			_clk_id, _parents##_idx, 0, _lock)
214 			     _clk_num, _gate_flags,  _clk_id, _flags)	\  argument
217 		.clk_id = _clk_id,					\