Lines Matching refs:GATE
213 #define GATE(_name, _parent_name, \ macro
513 GATE("rtc", "clk_32k", 4, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_rtc, 0),
514 GATE("timer", "clk_m", 5, 0, tegra_clk_timer, 0),
515 GATE("isp", "clk_m", 23, 0, tegra_clk_isp, 0),
516 GATE("vcp", "clk_m", 29, 0, tegra_clk_vcp, 0),
517 GATE("apbdma", "clk_m", 34, 0, tegra_clk_apbdma, 0),
518 GATE("kbc", "clk_32k", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0),
519 GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0),
520 GATE("fuse_burn", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse_burn, 0),
521 GATE("kfuse", "clk_m", 40, TEGRA_PERIPH_ON_APB, tegra_clk_kfuse, 0),
522 GATE("apbif", "clk_m", 107, TEGRA_PERIPH_ON_APB, tegra_clk_apbif, 0),
523 GATE("hda2hdmi", "clk_m", 128, TEGRA_PERIPH_ON_APB, tegra_clk_hda2hdmi, 0),
524 GATE("bsea", "clk_m", 62, 0, tegra_clk_bsea, 0),
525 GATE("bsev", "clk_m", 63, 0, tegra_clk_bsev, 0),
526 GATE("mipi-cal", "clk_m", 56, 0, tegra_clk_mipi_cal, 0),
527 GATE("usbd", "clk_m", 22, 0, tegra_clk_usbd, 0),
528 GATE("usb2", "clk_m", 58, 0, tegra_clk_usb2, 0),
529 GATE("usb3", "clk_m", 59, 0, tegra_clk_usb3, 0),
530 GATE("csi", "pll_p_out3", 52, 0, tegra_clk_csi, 0),
531 GATE("afi", "clk_m", 72, 0, tegra_clk_afi, 0),
532 GATE("csus", "clk_m", 92, TEGRA_PERIPH_NO_RESET, tegra_clk_csus, 0),
533 GATE("dds", "clk_m", 150, TEGRA_PERIPH_ON_APB, tegra_clk_dds, 0),
534 GATE("dp2", "clk_m", 152, TEGRA_PERIPH_ON_APB, tegra_clk_dp2, 0),
535 GATE("dtv", "clk_m", 79, TEGRA_PERIPH_ON_APB, tegra_clk_dtv, 0),
536 GATE("xusb_host", "xusb_host_src", 89, 0, tegra_clk_xusb_host, 0),
537 GATE("xusb_ss", "xusb_ss_src", 156, 0, tegra_clk_xusb_ss, 0),
538 GATE("xusb_dev", "xusb_dev_src", 95, 0, tegra_clk_xusb_dev, 0),
539 GATE("emc", "emc_mux", 57, 0, tegra_clk_emc, CLK_IGNORE_UNUSED),
540 GATE("sata_cold", "clk_m", 129, TEGRA_PERIPH_ON_APB, tegra_clk_sata_cold, 0),
541 GATE("ispb", "clk_m", 3, 0, tegra_clk_ispb, 0),
542 GATE("vim2_clk", "clk_m", 11, 0, tegra_clk_vim2_clk, 0),
543 GATE("pcie", "clk_m", 70, 0, tegra_clk_pcie, 0),
544 GATE("dpaux", "clk_m", 181, 0, tegra_clk_dpaux, 0),
545 GATE("gpu", "pll_ref", 184, 0, tegra_clk_gpu, 0),