44 	struct tegra_clk_super_mux *mux = to_clk_super_mux(hw);  in clk_super_get_parent()  local
48 	val = readl_relaxed(mux->reg);  in clk_super_get_parent()
55 		super_state_to_src_shift(mux, SUPER_STATE_IDLE) :  in clk_super_get_parent()
56 		super_state_to_src_shift(mux, SUPER_STATE_RUN);  in clk_super_get_parent()
58 	source = (val >> shift) & super_state_to_src_mask(mux);  in clk_super_get_parent()
64 	if ((mux->flags & TEGRA_DIVIDER_2) && !(val & SUPER_LP_DIV2_BYPASS) &&  in clk_super_get_parent()
65 	    (source == mux->pllx_index))  in clk_super_get_parent()
66 		source = mux->div2_index;  in clk_super_get_parent()
73 	struct tegra_clk_super_mux *mux = to_clk_super_mux(hw);  in clk_super_set_parent()  local
79 	if (mux->lock)  in clk_super_set_parent()
80 		spin_lock_irqsave(mux->lock, flags);  in clk_super_set_parent()
82 	val = readl_relaxed(mux->reg);  in clk_super_set_parent()
87 		super_state_to_src_shift(mux, SUPER_STATE_IDLE) :  in clk_super_set_parent()
88 		super_state_to_src_shift(mux, SUPER_STATE_RUN);  in clk_super_set_parent()
95 	if ((mux->flags & TEGRA_DIVIDER_2) && ((index == mux->div2_index) ||  in clk_super_set_parent()
96 					       (index == mux->pllx_index))) {  in clk_super_set_parent()
98 		if ((parent_index == mux->div2_index) ||  in clk_super_set_parent()
99 		    (parent_index == mux->pllx_index)) {  in clk_super_set_parent()
105 		writel_relaxed(val, mux->reg);  in clk_super_set_parent()
108 		if (index == mux->div2_index)  in clk_super_set_parent()
109 			index = mux->pllx_index;  in clk_super_set_parent()
111 	val &= ~((super_state_to_src_mask(mux)) << shift);  in clk_super_set_parent()
112 	val |= (index & (super_state_to_src_mask(mux))) << shift;  in clk_super_set_parent()
114 	writel_relaxed(val, mux->reg);  in clk_super_set_parent()
118 	if (mux->lock)  in clk_super_set_parent()
119 		spin_unlock_irqrestore(mux->lock, flags);  in clk_super_set_parent()