191 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)  macro
192 #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p)
193 #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)
887 	pll_writel(val, pll->params->iddq_reg, pll);  in clk_pll_iddq_enable()
913 	pll_writel(val, pll->params->iddq_reg, pll);  in clk_pll_iddq_disable()
1306 	pll_writel(val, pll->params->aux_reg, pll);  in clk_plle_tegra114_enable()
1320 	pll_writel(val, PLLE_SS_CTRL, pll);  in clk_plle_tegra114_enable()
1342 	pll_writel(val, PLLE_SS_CTRL, pll);  in clk_plle_tegra114_enable()
1344 	pll_writel(val, PLLE_SS_CTRL, pll);  in clk_plle_tegra114_enable()
1347 	pll_writel(val, PLLE_SS_CTRL, pll);  in clk_plle_tegra114_enable()
1358 	pll_writel(val, pll->params->aux_reg, pll);  in clk_plle_tegra114_enable()
1361 	pll_writel(val, pll->params->aux_reg, pll);  in clk_plle_tegra114_enable()
1368 	pll_writel(val, XUSBIO_PLL_CFG0, pll);  in clk_plle_tegra114_enable()
1371 	pll_writel(val, XUSBIO_PLL_CFG0, pll);  in clk_plle_tegra114_enable()
1378 	pll_writel(val, SATA_PLL_CFG0, pll);  in clk_plle_tegra114_enable()
1384 	pll_writel(val, SATA_PLL_CFG0, pll);  in clk_plle_tegra114_enable()
1756 	pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll);  in tegra_clk_register_pllc()
1757 	pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll);  in tegra_clk_register_pllc()
1758 	pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll);  in tegra_clk_register_pllc()
1798 		pll_writel(val_aux, pll_params->aux_reg, pll);  in tegra_clk_register_plle_tegra114()
1872 	pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll);  in tegra_clk_register_pllss()
1873 	pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll);  in tegra_clk_register_pllss()
1874 	pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll);  in tegra_clk_register_pllss()