823 static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,  in _pll_fixed_mdiv()  argument
826 	if (parent_rate > pll_params->cf_max)  in _pll_fixed_mdiv()
838 static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params,  in _setup_dynamic_ramp()  argument
867 	val = step_a << pll_params->stepa_shift;  in _setup_dynamic_ramp()
868 	val |= step_b << pll_params->stepb_shift;  in _setup_dynamic_ramp()
869 	writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg);  in _setup_dynamic_ramp()
1415 		void __iomem *pmc, struct tegra_clk_pll_params *pll_params,  in _tegra_init_pll()  argument
1427 	pll->params = pll_params;  in _tegra_init_pll()
1430 	if (!pll_params->div_nmp)  in _tegra_init_pll()
1431 		pll_params->div_nmp = &default_nmp;  in _tegra_init_pll()
1456 		unsigned long flags, struct tegra_clk_pll_params *pll_params,  in tegra_clk_register_pll()  argument
1462 	pll_params->flags |= TEGRA_PLL_BYPASS;  in tegra_clk_register_pll()
1463 	pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;  in tegra_clk_register_pll()
1464 	pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);  in tegra_clk_register_pll()
1487 		unsigned long flags, struct tegra_clk_pll_params *pll_params,  in tegra_clk_register_plle()  argument
1493 	pll_params->flags |= TEGRA_PLL_LOCK_MISC | TEGRA_PLL_BYPASS;  in tegra_clk_register_plle()
1494 	pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;  in tegra_clk_register_plle()
1496 	if (!pll_params->div_nmp)  in tegra_clk_register_plle()
1497 		pll_params->div_nmp = &pll_e_nmp;  in tegra_clk_register_plle()
1499 	pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);  in tegra_clk_register_plle()
1561 			  struct tegra_clk_pll_params *pll_params,  in tegra_clk_register_pllxc()  argument
1577 	if (!pll_params->pdiv_tohw)  in tegra_clk_register_pllxc()
1582 	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);  in tegra_clk_register_pllxc()
1584 	err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate);  in tegra_clk_register_pllxc()
1588 	val = readl_relaxed(clk_base + pll_params->base_reg);  in tegra_clk_register_pllxc()
1589 	val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);  in tegra_clk_register_pllxc()
1592 		WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx));  in tegra_clk_register_pllxc()
1594 		val_iddq |= BIT(pll_params->iddq_bit_idx);  in tegra_clk_register_pllxc()
1595 		writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);  in tegra_clk_register_pllxc()
1598 	pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;  in tegra_clk_register_pllxc()
1599 	pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);  in tegra_clk_register_pllxc()
1614 			  struct tegra_clk_pll_params *pll_params,  in tegra_clk_register_pllre()  argument
1621 	pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_LOCK_MISC;  in tegra_clk_register_pllre()
1623 	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);  in tegra_clk_register_pllre()
1625 	pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);  in tegra_clk_register_pllre()
1633 		WARN_ON(val & pll_params->iddq_bit_idx);  in tegra_clk_register_pllre()
1637 		m = _pll_fixed_mdiv(pll_params, parent_rate);  in tegra_clk_register_pllre()
1639 		val |= (pll_params->vco_min / parent_rate) << divn_shift(pll);  in tegra_clk_register_pllre()
1660 			  struct tegra_clk_pll_params *pll_params,  in tegra_clk_register_pllm()  argument
1667 	if (!pll_params->pdiv_tohw)  in tegra_clk_register_pllm()
1679 	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);  in tegra_clk_register_pllm()
1681 	pll_params->flags |= TEGRA_PLL_BYPASS;  in tegra_clk_register_pllm()
1682 	pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;  in tegra_clk_register_pllm()
1683 	pll_params->flags |= TEGRA_PLLM;  in tegra_clk_register_pllm()
1684 	pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);  in tegra_clk_register_pllm()
1699 			  struct tegra_clk_pll_params *pll_params,  in tegra_clk_register_pllc()  argument
1703 	struct pdiv_map *p_tohw = pll_params->pdiv_tohw;  in tegra_clk_register_pllc()
1720 	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);  in tegra_clk_register_pllc()
1722 	pll_params->flags |= TEGRA_PLL_BYPASS;  in tegra_clk_register_pllc()
1723 	pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);  in tegra_clk_register_pllc()
1736 	cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);  in tegra_clk_register_pllc()
1737 	cfg.n = cfg.m * pll_params->vco_min / parent_rate;  in tegra_clk_register_pllc()
1756 	pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll);  in tegra_clk_register_pllc()
1757 	pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll);  in tegra_clk_register_pllc()
1758 	pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll);  in tegra_clk_register_pllc()
1773 				struct tegra_clk_pll_params *pll_params,  in tegra_clk_register_plle_tegra114()  argument
1780 	pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;  in tegra_clk_register_plle_tegra114()
1781 	pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);  in tegra_clk_register_plle_tegra114()
1788 	val_aux = pll_readl(pll_params->aux_reg, pll);  in tegra_clk_register_plle_tegra114()
1798 		pll_writel(val_aux, pll_params->aux_reg, pll);  in tegra_clk_register_plle_tegra114()
1822 				struct tegra_clk_pll_params *pll_params,  in tegra_clk_register_pllss()  argument
1832 	if (!pll_params->div_nmp)  in tegra_clk_register_pllss()
1842 	pll_params->flags = TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_USE_LOCK;  in tegra_clk_register_pllss()
1843 	pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);  in tegra_clk_register_pllss()
1853 	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);  in tegra_clk_register_pllss()
1857 	cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);  in tegra_clk_register_pllss()
1858 	cfg.n = cfg.m * pll_params->vco_min / parent_rate;  in tegra_clk_register_pllss()
1860 	for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++)  in tegra_clk_register_pllss()
1867 	cfg.p = pll_params->pdiv_tohw[i-1].hw_val;  in tegra_clk_register_pllss()
1872 	pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll);  in tegra_clk_register_pllss()
1873 	pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll);  in tegra_clk_register_pllss()
1874 	pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll);  in tegra_clk_register_pllss()
1878 		if (val & BIT(pll_params->iddq_bit_idx)) {  in tegra_clk_register_pllss()
1884 		val |= BIT(pll_params->iddq_bit_idx);  in tegra_clk_register_pllss()