394 			   unsigned long rate, unsigned long parent_rate)  in _get_table_rate()  argument
400 		if (sel->input_rate == parent_rate &&  in _get_table_rate()
418 		      unsigned long rate, unsigned long parent_rate)  in _calc_rate()  argument
425 	switch (parent_rate) {  in _calc_rate()
442 		cfreq = parent_rate/(parent_rate/1000000);  in _calc_rate()
446 		       __func__, parent_rate);  in _calc_rate()
455 	cfg->m = parent_rate / cfreq;  in _calc_rate()
588 			unsigned long parent_rate)  in clk_pll_set_rate()  argument
605 	if (_get_table_rate(hw, &cfg, rate, parent_rate) &&  in clk_pll_set_rate()
606 	    _calc_rate(hw, &cfg, rate, parent_rate)) {  in clk_pll_set_rate()
647 					 unsigned long parent_rate)  in clk_pll_recalc_rate()  argument
652 	u64 rate = parent_rate;  in clk_pll_recalc_rate()
658 		return parent_rate;  in clk_pll_recalc_rate()
664 					parent_rate)) {  in clk_pll_recalc_rate()
786 					 unsigned long parent_rate)  in clk_plle_recalc_rate()  argument
791 	u64 rate = parent_rate;  in clk_plle_recalc_rate()
824 			   unsigned long parent_rate)  in _pll_fixed_mdiv()  argument
826 	if (parent_rate > pll_params->cf_max)  in _pll_fixed_mdiv()
833 				   unsigned long parent_rate)  in _clip_vco_min()  argument
835 	return DIV_ROUND_UP(vco_min, parent_rate) * parent_rate;  in _clip_vco_min()
840 			       unsigned long parent_rate)  in _setup_dynamic_ramp()  argument
845 	switch (parent_rate) {  in _setup_dynamic_ramp()
862 			__func__, parent_rate);  in _setup_dynamic_ramp()
922 				unsigned long rate, unsigned long parent_rate)  in _calc_dynamic_ramp_rate()  argument
932 	cfg->m = _pll_fixed_mdiv(pll->params, parent_rate);  in _calc_dynamic_ramp_rate()
934 	cfg->n = cfg->output_rate * cfg->m / parent_rate;  in _calc_dynamic_ramp_rate()
950 			      unsigned long rate, unsigned long parent_rate)  in _pll_ramp_calc_pll()  argument
955 	err = _get_table_rate(hw, cfg, rate, parent_rate);  in _pll_ramp_calc_pll()
957 		err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate);  in _pll_ramp_calc_pll()
959 		if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) {  in _pll_ramp_calc_pll()
979 				unsigned long parent_rate)  in clk_pllxc_set_rate()  argument
986 	ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);  in clk_pllxc_set_rate()
1026 				unsigned long parent_rate)  in clk_pllm_set_rate()  argument
1046 	ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);  in clk_pllm_set_rate()
1162 				unsigned long parent_rate)  in clk_pllc_set_rate()  argument
1172 	ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);  in clk_pllc_set_rate()
1190 	ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);  in clk_pllc_set_rate()
1208 			     unsigned long rate, unsigned long parent_rate)  in _pllre_calc_rate()  argument
1211 	u64 output_rate = parent_rate;  in _pllre_calc_rate()
1213 	m = _pll_fixed_mdiv(pll->params, parent_rate);  in _pllre_calc_rate()
1214 	n = rate * m / parent_rate;  in _pllre_calc_rate()
1228 				unsigned long parent_rate)  in clk_pllre_set_rate()  argument
1238 	_pllre_calc_rate(pll, &cfg, rate, parent_rate);  in clk_pllre_set_rate()
1262 					 unsigned long parent_rate)  in clk_pllre_recalc_rate()  argument
1266 	u64 rate = parent_rate;  in clk_pllre_recalc_rate()
1566 	unsigned long parent_rate;  in tegra_clk_register_pllxc()  local
1580 	parent_rate = clk_get_rate(parent);  in tegra_clk_register_pllxc()
1582 	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);  in tegra_clk_register_pllxc()
1584 	err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate);  in tegra_clk_register_pllxc()
1615 			  spinlock_t *lock, unsigned long parent_rate)  in tegra_clk_register_pllre()  argument
1623 	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);  in tegra_clk_register_pllre()
1637 		m = _pll_fixed_mdiv(pll_params, parent_rate);  in tegra_clk_register_pllre()
1639 		val |= (pll_params->vco_min / parent_rate) << divn_shift(pll);  in tegra_clk_register_pllre()
1665 	unsigned long parent_rate;  in tegra_clk_register_pllm()  local
1677 	parent_rate = clk_get_rate(parent);  in tegra_clk_register_pllm()
1679 	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);  in tegra_clk_register_pllm()
1706 	unsigned long parent_rate;  in tegra_clk_register_pllc()  local
1718 	parent_rate = clk_get_rate(parent);  in tegra_clk_register_pllc()
1720 	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);  in tegra_clk_register_pllc()
1736 	cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);  in tegra_clk_register_pllc()
1737 	cfg.n = cfg.m * pll_params->vco_min / parent_rate;  in tegra_clk_register_pllc()
1760 	_pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);  in tegra_clk_register_pllc()
1828 	unsigned long parent_rate;  in tegra_clk_register_pllss()  local
1851 	parent_rate = clk_get_rate(parent);  in tegra_clk_register_pllss()
1853 	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);  in tegra_clk_register_pllss()
1857 	cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);  in tegra_clk_register_pllss()
1858 	cfg.n = cfg.m * pll_params->vco_min / parent_rate;  in tegra_clk_register_pllss()