187 #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
188 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
192 #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p)
193 #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)
197 #define divm_mask(p) mask(p->params->div_nmp->divm_width)
198 #define divn_mask(p) mask(p->params->div_nmp->divn_width)
199 #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\
200 		      mask(p->params->div_nmp->divp_width))
202 #define divm_shift(p) (p)->params->div_nmp->divm_shift
203 #define divn_shift(p) (p)->params->div_nmp->divn_shift
204 #define divp_shift(p) (p)->params->div_nmp->divp_shift
227 	if (!(pll->params->flags & TEGRA_PLL_USE_LOCK))  in clk_pll_enable_lock()
230 	if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE))  in clk_pll_enable_lock()
234 	val |= BIT(pll->params->lock_enable_bit_idx);  in clk_pll_enable_lock()
244 	if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) {  in clk_pll_wait_for_lock()
245 		udelay(pll->params->lock_delay);  in clk_pll_wait_for_lock()
250 	if (pll->params->flags & TEGRA_PLL_LOCK_MISC)  in clk_pll_wait_for_lock()
251 		lock_addr += pll->params->misc_reg;  in clk_pll_wait_for_lock()
253 		lock_addr += pll->params->base_reg;  in clk_pll_wait_for_lock()
255 	lock_mask = pll->params->lock_mask;  in clk_pll_wait_for_lock()
257 	for (i = 0; i < pll->params->lock_delay; i++) {  in clk_pll_wait_for_lock()
277 	if (pll->params->flags & TEGRA_PLLM) {  in clk_pll_is_enabled()
296 	if (pll->params->flags & TEGRA_PLL_BYPASS)  in _clk_pll_enable()
301 	if (pll->params->flags & TEGRA_PLLM) {  in _clk_pll_enable()
314 	if (pll->params->flags & TEGRA_PLL_BYPASS)  in _clk_pll_disable()
319 	if (pll->params->flags & TEGRA_PLLM) {  in _clk_pll_disable()
362 	struct pdiv_map *p_tohw = pll->params->pdiv_tohw;  in _p_div_to_hw()
378 	struct pdiv_map *p_tohw = pll->params->pdiv_tohw;  in _hw_to_p_div()
399 	for (sel = pll->params->freq_table; sel->input_rate != 0; sel++)  in _get_table_rate()
461 	    || cfg->output_rate > pll->params->vco_max) {  in _calc_rate()
467 	if (pll->params->pdiv_tohw) {  in _calc_rate()
483 	struct tegra_clk_pll_params *params = pll->params;  in _update_pll_mnp()  local
484 	struct div_nmp *div_nmp = params->div_nmp;  in _update_pll_mnp()
486 	if ((params->flags & TEGRA_PLLM) &&  in _update_pll_mnp()
489 		val = pll_override_readl(params->pmc_divp_reg, pll);  in _update_pll_mnp()
492 		pll_override_writel(val, params->pmc_divp_reg, pll);  in _update_pll_mnp()
494 		val = pll_override_readl(params->pmc_divnm_reg, pll);  in _update_pll_mnp()
499 		pll_override_writel(val, params->pmc_divnm_reg, pll);  in _update_pll_mnp()
518 	struct tegra_clk_pll_params *params = pll->params;  in _get_pll_mnp()  local
519 	struct div_nmp *div_nmp = params->div_nmp;  in _get_pll_mnp()
521 	if ((params->flags & TEGRA_PLLM) &&  in _get_pll_mnp()
524 		val = pll_override_readl(params->pmc_divp_reg, pll);  in _get_pll_mnp()
527 		val = pll_override_readl(params->pmc_divnm_reg, pll);  in _get_pll_mnp()
550 	if (pll->params->flags & TEGRA_PLL_SET_LFCON) {  in _update_pll_cpcon()
554 	} else if (pll->params->flags & TEGRA_PLL_SET_DCCON) {  in _update_pll_cpcon()
556 		if (rate >= (pll->params->vco_max >> 1))  in _update_pll_cpcon()
576 	if (pll->params->flags & TEGRA_PLL_HAS_CPCON)  in _program_pll()
595 	if (pll->params->flags & TEGRA_PLL_FIXED) {  in clk_pll_set_rate()
596 		if (rate != pll->params->fixed_rate) {  in clk_pll_set_rate()
599 				pll->params->fixed_rate, rate);  in clk_pll_set_rate()
632 	if (pll->params->flags & TEGRA_PLL_FIXED)  in clk_pll_round_rate()
633 		return pll->params->fixed_rate;  in clk_pll_round_rate()
636 	if (pll->params->flags & TEGRA_PLLM)  in clk_pll_round_rate()
657 	if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS))  in clk_pll_recalc_rate()
660 	if ((pll->params->flags & TEGRA_PLL_FIXED) &&  in clk_pll_recalc_rate()
663 		if (_get_table_rate(hw, &sel, pll->params->fixed_rate,  in clk_pll_recalc_rate()
669 		return pll->params->fixed_rate;  in clk_pll_recalc_rate()
737 	if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))  in clk_plle_enable()
753 	if (pll->params->flags & TEGRA_PLLE_CONFIGURE) {  in clk_plle_enable()
793 	divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll));  in clk_plle_recalc_rate()
794 	divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll));  in clk_plle_recalc_rate()
795 	divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll));  in clk_plle_recalc_rate()
885 	val = pll_readl(pll->params->iddq_reg, pll);  in clk_pll_iddq_enable()
886 	val &= ~BIT(pll->params->iddq_bit_idx);  in clk_pll_iddq_enable()
887 	pll_writel(val, pll->params->iddq_reg, pll);  in clk_pll_iddq_enable()
911 	val = pll_readl(pll->params->iddq_reg, pll);  in clk_pll_iddq_disable()
912 	val |= BIT(pll->params->iddq_bit_idx);  in clk_pll_iddq_disable()
913 	pll_writel(val, pll->params->iddq_reg, pll);  in clk_pll_iddq_disable()
931 	p = DIV_ROUND_UP(pll->params->vco_min, rate);  in _calc_dynamic_ramp_rate()
932 	cfg->m = _pll_fixed_mdiv(pll->params, parent_rate);  in _calc_dynamic_ramp_rate()
942 	if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max)  in _calc_dynamic_ramp_rate()
959 		if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) {  in _pll_ramp_calc_pll()
971 	if (cfg->p >  pll->params->max_p)  in _pll_ramp_calc_pll()
1213 	m = _pll_fixed_mdiv(pll->params, parent_rate);  in _pllre_calc_rate()
1293 	if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))  in clk_plle_tegra114_enable()
1303 	val = pll_readl(pll->params->aux_reg, pll);  in clk_plle_tegra114_enable()
1306 	pll_writel(val, pll->params->aux_reg, pll);  in clk_plle_tegra114_enable()
1355 	val = pll_readl(pll->params->aux_reg, pll);  in clk_plle_tegra114_enable()
1358 	pll_writel(val, pll->params->aux_reg, pll);  in clk_plle_tegra114_enable()
1361 	pll_writel(val, pll->params->aux_reg, pll);  in clk_plle_tegra114_enable()
1427 	pll->params = pll_params;  in _tegra_init_pll()