393 			   struct tegra_clk_pll_freq_table *cfg,  in _get_table_rate()  argument
407 	cfg->input_rate = sel->input_rate;  in _get_table_rate()
408 	cfg->output_rate = sel->output_rate;  in _get_table_rate()
409 	cfg->m = sel->m;  in _get_table_rate()
410 	cfg->n = sel->n;  in _get_table_rate()
411 	cfg->p = sel->p;  in _get_table_rate()
412 	cfg->cpcon = sel->cpcon;  in _get_table_rate()
417 static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,  in _calc_rate()  argument
451 	for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq;  in _calc_rate()
452 	     cfg->output_rate <<= 1)  in _calc_rate()
455 	cfg->m = parent_rate / cfreq;  in _calc_rate()
456 	cfg->n = cfg->output_rate / cfreq;  in _calc_rate()
457 	cfg->cpcon = OUT_OF_TABLE_CPCON;  in _calc_rate()
459 	if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) ||  in _calc_rate()
461 	    || cfg->output_rate > pll->params->vco_max) {  in _calc_rate()
465 	cfg->output_rate >>= p_div;  in _calc_rate()
472 			cfg->p = ret;  in _calc_rate()
474 		cfg->p = p_div;  in _calc_rate()
480 			    struct tegra_clk_pll_freq_table *cfg)  in _update_pll_mnp()  argument
491 		val |= cfg->p << div_nmp->override_divp_shift;  in _update_pll_mnp()
497 		val |= (cfg->m << div_nmp->override_divm_shift) |  in _update_pll_mnp()
498 			(cfg->n << div_nmp->override_divn_shift);  in _update_pll_mnp()
506 		val |= (cfg->m << divm_shift(pll)) |  in _update_pll_mnp()
507 		       (cfg->n << divn_shift(pll)) |  in _update_pll_mnp()
508 		       (cfg->p << divp_shift(pll));  in _update_pll_mnp()
515 			 struct tegra_clk_pll_freq_table *cfg)  in _get_pll_mnp()  argument
525 		cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll);  in _get_pll_mnp()
528 		cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll);  in _get_pll_mnp()
529 		cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll);  in _get_pll_mnp()
533 		cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll);  in _get_pll_mnp()
534 		cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll);  in _get_pll_mnp()
535 		cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll);  in _get_pll_mnp()
540 			      struct tegra_clk_pll_freq_table *cfg,  in _update_pll_cpcon()  argument
548 	val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT;  in _update_pll_cpcon()
552 		if (cfg->n >= PLLDU_LFCON_SET_DIVN)  in _update_pll_cpcon()
563 static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,  in _program_pll()  argument
574 	_update_pll_mnp(pll, cfg);  in _program_pll()
577 		_update_pll_cpcon(pll, cfg, rate);  in _program_pll()
591 	struct tegra_clk_pll_freq_table cfg, old_cfg;  in clk_pll_set_rate()  local
605 	if (_get_table_rate(hw, &cfg, rate, parent_rate) &&  in clk_pll_set_rate()
606 	    _calc_rate(hw, &cfg, rate, parent_rate)) {  in clk_pll_set_rate()
617 	if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p)  in clk_pll_set_rate()
618 		ret = _program_pll(hw, &cfg, rate);  in clk_pll_set_rate()
630 	struct tegra_clk_pll_freq_table cfg;  in clk_pll_round_rate()  local
639 	if (_get_table_rate(hw, &cfg, rate, *prate) &&  in clk_pll_round_rate()
640 	    _calc_rate(hw, &cfg, rate, *prate))  in clk_pll_round_rate()
643 	return cfg.output_rate;  in clk_pll_round_rate()
650 	struct tegra_clk_pll_freq_table cfg;  in clk_pll_recalc_rate()  local
672 	_get_pll_mnp(pll, &cfg);  in clk_pll_recalc_rate()
674 	pdiv = _hw_to_p_div(hw, cfg.p);  in clk_pll_recalc_rate()
680 	cfg.m *= pdiv;  in clk_pll_recalc_rate()
682 	rate *= cfg.n;  in clk_pll_recalc_rate()
683 	do_div(rate, cfg.m);  in clk_pll_recalc_rate()
921 				struct tegra_clk_pll_freq_table *cfg,  in _calc_dynamic_ramp_rate()  argument
932 	cfg->m = _pll_fixed_mdiv(pll->params, parent_rate);  in _calc_dynamic_ramp_rate()
933 	cfg->output_rate = rate * p;  in _calc_dynamic_ramp_rate()
934 	cfg->n = cfg->output_rate * cfg->m / parent_rate;  in _calc_dynamic_ramp_rate()
940 		cfg->p = p_div;  in _calc_dynamic_ramp_rate()
942 	if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max)  in _calc_dynamic_ramp_rate()
949 			      struct tegra_clk_pll_freq_table *cfg,  in _pll_ramp_calc_pll()  argument
955 	err = _get_table_rate(hw, cfg, rate, parent_rate);  in _pll_ramp_calc_pll()
957 		err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate);  in _pll_ramp_calc_pll()
959 		if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) {  in _pll_ramp_calc_pll()
964 		p_div = _p_div_to_hw(hw, cfg->p);  in _pll_ramp_calc_pll()
968 			cfg->p = p_div;  in _pll_ramp_calc_pll()
971 	if (cfg->p >  pll->params->max_p)  in _pll_ramp_calc_pll()
982 	struct tegra_clk_pll_freq_table cfg, old_cfg;  in clk_pllxc_set_rate()  local
986 	ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);  in clk_pllxc_set_rate()
995 	if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p)  in clk_pllxc_set_rate()
996 		ret = _program_pll(hw, &cfg, rate);  in clk_pllxc_set_rate()
1007 	struct tegra_clk_pll_freq_table cfg;  in clk_pll_ramp_round_rate()  local
1011 	ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate);  in clk_pll_ramp_round_rate()
1015 	p_div = _hw_to_p_div(hw, cfg.p);  in clk_pll_ramp_round_rate()
1019 	output_rate *= cfg.n;  in clk_pll_ramp_round_rate()
1020 	do_div(output_rate, cfg.m * p_div);  in clk_pll_ramp_round_rate()
1028 	struct tegra_clk_pll_freq_table cfg;  in clk_pllm_set_rate()  local
1046 	ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);  in clk_pllm_set_rate()
1050 	_update_pll_mnp(pll, &cfg);  in clk_pllm_set_rate()
1164 	struct tegra_clk_pll_freq_table cfg, old_cfg;  in clk_pllc_set_rate()  local
1172 	ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);  in clk_pllc_set_rate()
1178 	if (cfg.m != old_cfg.m) {  in clk_pllc_set_rate()
1183 	if (old_cfg.n == cfg.n && old_cfg.p == cfg.p)  in clk_pllc_set_rate()
1190 	ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);  in clk_pllc_set_rate()
1194 	_update_pll_mnp(pll, &cfg);  in clk_pllc_set_rate()
1207 			     struct tegra_clk_pll_freq_table *cfg,  in _pllre_calc_rate()  argument
1219 	if (cfg) {  in _pllre_calc_rate()
1220 		cfg->m = m;  in _pllre_calc_rate()
1221 		cfg->n = n;  in _pllre_calc_rate()
1230 	struct tegra_clk_pll_freq_table cfg, old_cfg;  in clk_pllre_set_rate()  local
1238 	_pllre_calc_rate(pll, &cfg, rate, parent_rate);  in clk_pllre_set_rate()
1240 	cfg.p = old_cfg.p;  in clk_pllre_set_rate()
1242 	if (cfg.m != old_cfg.m || cfg.n != old_cfg.n) {  in clk_pllre_set_rate()
1247 		_update_pll_mnp(pll, &cfg);  in clk_pllre_set_rate()
1264 	struct tegra_clk_pll_freq_table cfg;  in clk_pllre_recalc_rate()  local
1268 	_get_pll_mnp(pll, &cfg);  in clk_pllre_recalc_rate()
1270 	rate *= cfg.n;  in clk_pllre_recalc_rate()
1271 	do_div(rate, cfg.m);  in clk_pllre_recalc_rate()
1705 	struct tegra_clk_pll_freq_table cfg;  in tegra_clk_register_pllc()  local
1736 	cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);  in tegra_clk_register_pllc()
1737 	cfg.n = cfg.m * pll_params->vco_min / parent_rate;  in tegra_clk_register_pllc()
1741 			cfg.p = p_tohw->hw_val;  in tegra_clk_register_pllc()
1753 	_update_pll_mnp(pll, &cfg);  in tegra_clk_register_pllc()
1760 	_pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);  in tegra_clk_register_pllc()
1827 	struct tegra_clk_pll_freq_table cfg;  in tegra_clk_register_pllss()  local
1857 	cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);  in tegra_clk_register_pllss()
1858 	cfg.n = cfg.m * pll_params->vco_min / parent_rate;  in tegra_clk_register_pllss()
1867 	cfg.p = pll_params->pdiv_tohw[i-1].hw_val;  in tegra_clk_register_pllss()
1869 	_update_pll_mnp(pll, &cfg);  in tegra_clk_register_pllss()