123 	struct emc_timing *timing = NULL;  in emc_determine_rate()  local
132 		timing = tegra->timings + i;  in emc_determine_rate()
134 		if (timing->rate > req->max_rate) {  in emc_determine_rate()
140 		if (timing->rate < req->min_rate)  in emc_determine_rate()
143 		if (timing->rate >= req->rate) {  in emc_determine_rate()
144 			req->rate = timing->rate;  in emc_determine_rate()
149 	if (timing) {  in emc_determine_rate()
150 		req->rate = timing->rate;  in emc_determine_rate()
201 			  struct emc_timing *timing)  in emc_set_timing()  argument
212 	pr_debug("going to rate %ld prate %ld p %s\n", timing->rate,  in emc_set_timing()
213 		 timing->parent_rate, __clk_get_name(timing->parent));  in emc_set_timing()
215 	if (emc_get_parent(&tegra->hw) == timing->parent_index &&  in emc_set_timing()
216 	    clk_get_rate(timing->parent) != timing->parent_rate) {  in emc_set_timing()
223 	err = clk_set_rate(timing->parent, timing->parent_rate);  in emc_set_timing()
226 		       __clk_get_name(timing->parent), timing->parent_rate,  in emc_set_timing()
232 	err = clk_prepare_enable(timing->parent);  in emc_set_timing()
238 	div = timing->parent_rate / (timing->rate / 2) - 2;  in emc_set_timing()
240 	err = tegra_emc_prepare_timing_change(emc, timing->rate);  in emc_set_timing()
249 	car_value |= CLK_SOURCE_EMC_EMC_2X_CLK_SRC(timing->parent_index);  in emc_set_timing()
258 	tegra_emc_complete_timing_change(emc, timing->rate);  in emc_set_timing()
260 	clk_hw_reparent(&tegra->hw, __clk_get_hw(timing->parent));  in emc_set_timing()
263 	tegra->prev_parent = timing->parent;  in emc_set_timing()
280 	struct emc_timing *timing;  in get_backup_timing()  local
283 		timing = tegra->timings + i;  in get_backup_timing()
284 		if (timing->ram_code != ram_code)  in get_backup_timing()
287 		if (emc_parent_clk_sources[timing->parent_index] !=  in get_backup_timing()
290 			return timing;  in get_backup_timing()
294 		timing = tegra->timings + i;  in get_backup_timing()
295 		if (timing->ram_code != ram_code)  in get_backup_timing()
298 		if (emc_parent_clk_sources[timing->parent_index] !=  in get_backup_timing()
301 			return timing;  in get_backup_timing()
311 	struct emc_timing *timing = NULL;  in emc_set_rate()  local
331 			timing = tegra->timings + i;  in emc_set_rate()
336 	if (!timing) {  in emc_set_rate()
342 	    emc_parent_clk_sources[timing->parent_index] &&  in emc_set_rate()
343 	    clk_get_rate(timing->parent) != timing->parent_rate) {  in emc_set_rate()
367 	return emc_set_timing(tegra, timing);  in emc_set_rate()
373 				   struct emc_timing *timing,  in load_one_timing_from_dt()  argument
385 	timing->rate = tmp;  in load_one_timing_from_dt()
394 	timing->parent_rate = tmp;  in load_one_timing_from_dt()
396 	timing->parent = of_clk_get_by_name(node, "emc-parent");  in load_one_timing_from_dt()
397 	if (IS_ERR(timing->parent)) {  in load_one_timing_from_dt()
400 		return PTR_ERR(timing->parent);  in load_one_timing_from_dt()
403 	timing->parent_index = 0xff;  in load_one_timing_from_dt()
406 			    __clk_get_name(timing->parent))) {  in load_one_timing_from_dt()
407 			timing->parent_index = i;  in load_one_timing_from_dt()
411 	if (timing->parent_index == 0xff) {  in load_one_timing_from_dt()
413 		       node->full_name, __clk_get_name(timing->parent));  in load_one_timing_from_dt()
414 		clk_put(timing->parent);  in load_one_timing_from_dt()
450 		struct emc_timing *timing = tegra->timings + (i++);  in load_timings_from_dt()  local
452 		err = load_one_timing_from_dt(tegra, timing, child);  in load_timings_from_dt()
456 		timing->ram_code = ram_code;  in load_timings_from_dt()