Lines Matching refs:td
322 static inline u32 dfll_readl(struct tegra_dfll *td, u32 offs) in dfll_readl() argument
324 return __raw_readl(td->base + offs); in dfll_readl()
327 static inline void dfll_writel(struct tegra_dfll *td, u32 val, u32 offs) in dfll_writel() argument
330 __raw_writel(val, td->base + offs); in dfll_writel()
333 static inline void dfll_wmb(struct tegra_dfll *td) in dfll_wmb() argument
335 dfll_readl(td, DFLL_CTRL); in dfll_wmb()
340 static inline u32 dfll_i2c_readl(struct tegra_dfll *td, u32 offs) in dfll_i2c_readl() argument
342 return __raw_readl(td->i2c_base + offs); in dfll_i2c_readl()
345 static inline void dfll_i2c_writel(struct tegra_dfll *td, u32 val, u32 offs) in dfll_i2c_writel() argument
347 __raw_writel(val, td->i2c_base + offs); in dfll_i2c_writel()
350 static inline void dfll_i2c_wmb(struct tegra_dfll *td) in dfll_i2c_wmb() argument
352 dfll_i2c_readl(td, DFLL_I2C_CFG); in dfll_i2c_wmb()
362 static bool dfll_is_running(struct tegra_dfll *td) in dfll_is_running() argument
364 return td->mode >= DFLL_OPEN_LOOP; in dfll_is_running()
382 struct tegra_dfll *td = dev_get_drvdata(dev); in tegra_dfll_runtime_resume() local
385 ret = clk_enable(td->ref_clk); in tegra_dfll_runtime_resume()
391 ret = clk_enable(td->soc_clk); in tegra_dfll_runtime_resume()
394 clk_disable(td->ref_clk); in tegra_dfll_runtime_resume()
398 ret = clk_enable(td->i2c_clk); in tegra_dfll_runtime_resume()
401 clk_disable(td->soc_clk); in tegra_dfll_runtime_resume()
402 clk_disable(td->ref_clk); in tegra_dfll_runtime_resume()
419 struct tegra_dfll *td = dev_get_drvdata(dev); in tegra_dfll_runtime_suspend() local
421 clk_disable(td->ref_clk); in tegra_dfll_runtime_suspend()
422 clk_disable(td->soc_clk); in tegra_dfll_runtime_suspend()
423 clk_disable(td->i2c_clk); in tegra_dfll_runtime_suspend()
441 static void dfll_tune_low(struct tegra_dfll *td) in dfll_tune_low() argument
443 td->tune_range = DFLL_TUNE_LOW; in dfll_tune_low()
445 dfll_writel(td, td->soc->tune0_low, DFLL_TUNE0); in dfll_tune_low()
446 dfll_writel(td, td->soc->tune1, DFLL_TUNE1); in dfll_tune_low()
447 dfll_wmb(td); in dfll_tune_low()
449 if (td->soc->set_clock_trimmers_low) in dfll_tune_low()
450 td->soc->set_clock_trimmers_low(); in dfll_tune_low()
483 static void dfll_set_mode(struct tegra_dfll *td, in dfll_set_mode() argument
486 td->mode = mode; in dfll_set_mode()
487 dfll_writel(td, mode - 1, DFLL_CTRL); in dfll_set_mode()
488 dfll_wmb(td); in dfll_set_mode()
503 static int dfll_i2c_set_output_enabled(struct tegra_dfll *td, bool enable) in dfll_i2c_set_output_enabled() argument
507 val = dfll_i2c_readl(td, DFLL_OUTPUT_CFG); in dfll_i2c_set_output_enabled()
514 dfll_i2c_writel(td, val, DFLL_OUTPUT_CFG); in dfll_i2c_set_output_enabled()
515 dfll_i2c_wmb(td); in dfll_i2c_set_output_enabled()
527 static void dfll_load_i2c_lut(struct tegra_dfll *td) in dfll_load_i2c_lut() argument
533 if (i < td->lut_min) in dfll_load_i2c_lut()
534 lut_index = td->lut_min; in dfll_load_i2c_lut()
535 else if (i > td->lut_max) in dfll_load_i2c_lut()
536 lut_index = td->lut_max; in dfll_load_i2c_lut()
540 val = regulator_list_hardware_vsel(td->vdd_reg, in dfll_load_i2c_lut()
541 td->i2c_lut[lut_index]); in dfll_load_i2c_lut()
542 __raw_writel(val, td->lut_base + i * 4); in dfll_load_i2c_lut()
545 dfll_i2c_wmb(td); in dfll_load_i2c_lut()
558 static void dfll_init_i2c_if(struct tegra_dfll *td) in dfll_init_i2c_if() argument
562 if (td->i2c_slave_addr > 0x7f) { in dfll_init_i2c_if()
563 val = td->i2c_slave_addr << DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_10BIT; in dfll_init_i2c_if()
566 val = td->i2c_slave_addr << DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_7BIT; in dfll_init_i2c_if()
570 dfll_i2c_writel(td, val, DFLL_I2C_CFG); in dfll_init_i2c_if()
572 dfll_i2c_writel(td, td->i2c_reg, DFLL_I2C_VDD_REG_ADDR); in dfll_init_i2c_if()
574 val = DIV_ROUND_UP(td->i2c_clk_rate, td->i2c_fs_rate * 8); in dfll_init_i2c_if()
580 __raw_writel(val, td->i2c_controller_base + DFLL_I2C_CLK_DIVISOR); in dfll_init_i2c_if()
581 dfll_i2c_wmb(td); in dfll_init_i2c_if()
592 static void dfll_init_out_if(struct tegra_dfll *td) in dfll_init_out_if() argument
596 td->lut_min = 0; in dfll_init_out_if()
597 td->lut_max = td->i2c_lut_size - 1; in dfll_init_out_if()
598 td->lut_safe = td->lut_min + 1; in dfll_init_out_if()
600 dfll_i2c_writel(td, 0, DFLL_OUTPUT_CFG); in dfll_init_out_if()
601 val = (td->lut_safe << DFLL_OUTPUT_CFG_SAFE_SHIFT) | in dfll_init_out_if()
602 (td->lut_max << DFLL_OUTPUT_CFG_MAX_SHIFT) | in dfll_init_out_if()
603 (td->lut_min << DFLL_OUTPUT_CFG_MIN_SHIFT); in dfll_init_out_if()
604 dfll_i2c_writel(td, val, DFLL_OUTPUT_CFG); in dfll_init_out_if()
605 dfll_i2c_wmb(td); in dfll_init_out_if()
607 dfll_writel(td, 0, DFLL_OUTPUT_FORCE); in dfll_init_out_if()
608 dfll_i2c_writel(td, 0, DFLL_INTR_EN); in dfll_init_out_if()
609 dfll_i2c_writel(td, DFLL_INTR_MAX_MASK | DFLL_INTR_MIN_MASK, in dfll_init_out_if()
612 dfll_load_i2c_lut(td); in dfll_init_out_if()
613 dfll_init_i2c_if(td); in dfll_init_out_if()
630 static int find_lut_index_for_rate(struct tegra_dfll *td, unsigned long rate) in find_lut_index_for_rate() argument
637 opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate); in find_lut_index_for_rate()
646 for (i = 0; i < td->i2c_lut_size; i++) { in find_lut_index_for_rate()
647 if (regulator_list_voltage(td->vdd_reg, td->i2c_lut[i]) == uv) in find_lut_index_for_rate()
665 static int dfll_calculate_rate_request(struct tegra_dfll *td, in dfll_calculate_rate_request() argument
678 if (rate < td->dvco_rate_min) { in dfll_calculate_rate_request()
682 td->dvco_rate_min / 1000); in dfll_calculate_rate_request()
684 dev_err(td->dev, "%s: Rate %lu is too low\n", in dfll_calculate_rate_request()
689 rate = td->dvco_rate_min; in dfll_calculate_rate_request()
693 val = DVCO_RATE_TO_MULT(rate, td->ref_rate); in dfll_calculate_rate_request()
695 dev_err(td->dev, "%s: Rate %lu is above dfll range\n", in dfll_calculate_rate_request()
700 req->dvco_target_rate = MULT_TO_DVCO_RATE(req->mult_bits, td->ref_rate); in dfll_calculate_rate_request()
703 req->lut_index = find_lut_index_for_rate(td, req->dvco_target_rate); in dfll_calculate_rate_request()
718 static void dfll_set_frequency_request(struct tegra_dfll *td, in dfll_set_frequency_request() argument
725 force_val = (req->lut_index - td->lut_safe) * coef / td->cg; in dfll_set_frequency_request()
734 dfll_writel(td, val, DFLL_FREQ_REQ); in dfll_set_frequency_request()
735 dfll_wmb(td); in dfll_set_frequency_request()
750 static int dfll_request_rate(struct tegra_dfll *td, unsigned long rate) in dfll_request_rate() argument
755 if (td->mode == DFLL_UNINITIALIZED) { in dfll_request_rate()
756 dev_err(td->dev, "%s: Cannot set DFLL rate in %s mode\n", in dfll_request_rate()
757 __func__, mode_name[td->mode]); in dfll_request_rate()
761 ret = dfll_calculate_rate_request(td, &req, rate); in dfll_request_rate()
765 td->last_unrounded_rate = rate; in dfll_request_rate()
766 td->last_req = req; in dfll_request_rate()
768 if (td->mode == DFLL_CLOSED_LOOP) in dfll_request_rate()
769 dfll_set_frequency_request(td, &td->last_req); in dfll_request_rate()
785 static int dfll_disable(struct tegra_dfll *td) in dfll_disable() argument
787 if (td->mode != DFLL_OPEN_LOOP) { in dfll_disable()
788 dev_err(td->dev, "cannot disable DFLL in %s mode\n", in dfll_disable()
789 mode_name[td->mode]); in dfll_disable()
793 dfll_set_mode(td, DFLL_DISABLED); in dfll_disable()
794 pm_runtime_put_sync(td->dev); in dfll_disable()
806 static int dfll_enable(struct tegra_dfll *td) in dfll_enable() argument
808 if (td->mode != DFLL_DISABLED) { in dfll_enable()
809 dev_err(td->dev, "cannot enable DFLL in %s mode\n", in dfll_enable()
810 mode_name[td->mode]); in dfll_enable()
814 pm_runtime_get_sync(td->dev); in dfll_enable()
815 dfll_set_mode(td, DFLL_OPEN_LOOP); in dfll_enable()
831 static void dfll_set_open_loop_config(struct tegra_dfll *td) in dfll_set_open_loop_config() argument
836 if (td->tune_range != DFLL_TUNE_LOW) in dfll_set_open_loop_config()
837 dfll_tune_low(td); in dfll_set_open_loop_config()
839 val = dfll_readl(td, DFLL_FREQ_REQ); in dfll_set_open_loop_config()
842 dfll_writel(td, val, DFLL_FREQ_REQ); in dfll_set_open_loop_config()
843 dfll_wmb(td); in dfll_set_open_loop_config()
854 static int dfll_lock(struct tegra_dfll *td) in dfll_lock() argument
856 struct dfll_rate_req *req = &td->last_req; in dfll_lock()
858 switch (td->mode) { in dfll_lock()
864 dev_err(td->dev, "%s: Cannot lock DFLL at rate 0\n", in dfll_lock()
869 dfll_i2c_set_output_enabled(td, true); in dfll_lock()
870 dfll_set_mode(td, DFLL_CLOSED_LOOP); in dfll_lock()
871 dfll_set_frequency_request(td, req); in dfll_lock()
875 BUG_ON(td->mode > DFLL_CLOSED_LOOP); in dfll_lock()
876 dev_err(td->dev, "%s: Cannot lock DFLL in %s mode\n", in dfll_lock()
877 __func__, mode_name[td->mode]); in dfll_lock()
889 static int dfll_unlock(struct tegra_dfll *td) in dfll_unlock() argument
891 switch (td->mode) { in dfll_unlock()
893 dfll_set_open_loop_config(td); in dfll_unlock()
894 dfll_set_mode(td, DFLL_OPEN_LOOP); in dfll_unlock()
895 dfll_i2c_set_output_enabled(td, false); in dfll_unlock()
902 BUG_ON(td->mode > DFLL_CLOSED_LOOP); in dfll_unlock()
903 dev_err(td->dev, "%s: Cannot unlock DFLL in %s mode\n", in dfll_unlock()
904 __func__, mode_name[td->mode]); in dfll_unlock()
920 struct tegra_dfll *td = clk_hw_to_dfll(hw); in dfll_clk_is_enabled() local
922 return dfll_is_running(td); in dfll_clk_is_enabled()
927 struct tegra_dfll *td = clk_hw_to_dfll(hw); in dfll_clk_enable() local
930 ret = dfll_enable(td); in dfll_clk_enable()
934 ret = dfll_lock(td); in dfll_clk_enable()
936 dfll_disable(td); in dfll_clk_enable()
943 struct tegra_dfll *td = clk_hw_to_dfll(hw); in dfll_clk_disable() local
946 ret = dfll_unlock(td); in dfll_clk_disable()
948 dfll_disable(td); in dfll_clk_disable()
954 struct tegra_dfll *td = clk_hw_to_dfll(hw); in dfll_clk_recalc_rate() local
956 return td->last_unrounded_rate; in dfll_clk_recalc_rate()
963 struct tegra_dfll *td = clk_hw_to_dfll(hw); in dfll_clk_determine_rate() local
967 ret = dfll_calculate_rate_request(td, &req, clk_req->rate); in dfll_clk_determine_rate()
983 struct tegra_dfll *td = clk_hw_to_dfll(hw); in dfll_clk_set_rate() local
985 return dfll_request_rate(td, rate); in dfll_clk_set_rate()
1011 static int dfll_register_clk(struct tegra_dfll *td) in dfll_register_clk() argument
1015 dfll_clk_init_data.name = td->output_clock_name; in dfll_register_clk()
1016 td->dfll_clk_hw.init = &dfll_clk_init_data; in dfll_register_clk()
1018 td->dfll_clk = clk_register(td->dev, &td->dfll_clk_hw); in dfll_register_clk()
1019 if (IS_ERR(td->dfll_clk)) { in dfll_register_clk()
1020 dev_err(td->dev, "DFLL clock registration error\n"); in dfll_register_clk()
1024 ret = of_clk_add_provider(td->dev->of_node, of_clk_src_simple_get, in dfll_register_clk()
1025 td->dfll_clk); in dfll_register_clk()
1027 dev_err(td->dev, "of_clk_add_provider() failed\n"); in dfll_register_clk()
1029 clk_unregister(td->dfll_clk); in dfll_register_clk()
1043 static void dfll_unregister_clk(struct tegra_dfll *td) in dfll_unregister_clk() argument
1045 of_clk_del_provider(td->dev->of_node); in dfll_unregister_clk()
1046 clk_unregister(td->dfll_clk); in dfll_unregister_clk()
1047 td->dfll_clk = NULL; in dfll_unregister_clk()
1086 static u64 dfll_read_monitor_rate(struct tegra_dfll *td) in dfll_read_monitor_rate() argument
1091 if (!dfll_is_running(td)) in dfll_read_monitor_rate()
1094 v = dfll_readl(td, DFLL_MONITOR_DATA); in dfll_read_monitor_rate()
1096 pre_scaler_rate = dfll_calc_monitored_rate(v, td->ref_rate); in dfll_read_monitor_rate()
1098 s = dfll_readl(td, DFLL_FREQ_REQ); in dfll_read_monitor_rate()
1107 struct tegra_dfll *td = data; in attr_enable_get() local
1109 *val = dfll_is_running(td); in attr_enable_get()
1115 struct tegra_dfll *td = data; in attr_enable_set() local
1117 return val ? dfll_enable(td) : dfll_disable(td); in attr_enable_set()
1124 struct tegra_dfll *td = data; in attr_lock_get() local
1126 *val = (td->mode == DFLL_CLOSED_LOOP); in attr_lock_get()
1132 struct tegra_dfll *td = data; in attr_lock_set() local
1134 return val ? dfll_lock(td) : dfll_unlock(td); in attr_lock_set()
1141 struct tegra_dfll *td = data; in attr_rate_get() local
1143 *val = dfll_read_monitor_rate(td); in attr_rate_get()
1150 struct tegra_dfll *td = data; in attr_rate_set() local
1152 return dfll_request_rate(td, val); in attr_rate_set()
1159 struct tegra_dfll *td = s->private; in attr_registers_show() local
1164 val = dfll_i2c_readl(td, offs); in attr_registers_show()
1166 val = dfll_readl(td, offs); in attr_registers_show()
1173 dfll_i2c_readl(td, offs)); in attr_registers_show()
1176 dfll_i2c_readl(td, offs)); in attr_registers_show()
1181 __raw_readl(td->i2c_controller_base + offs)); in attr_registers_show()
1186 __raw_readl(td->lut_base + offs)); in attr_registers_show()
1203 static int dfll_debug_init(struct tegra_dfll *td) in dfll_debug_init() argument
1207 if (!td || (td->mode == DFLL_UNINITIALIZED)) in dfll_debug_init()
1210 td->debugfs_dir = debugfs_create_dir("tegra_dfll_fcpu", NULL); in dfll_debug_init()
1211 if (!td->debugfs_dir) in dfll_debug_init()
1217 td->debugfs_dir, td, &enable_fops)) in dfll_debug_init()
1221 td->debugfs_dir, td, &lock_fops)) in dfll_debug_init()
1225 td->debugfs_dir, td, &rate_fops)) in dfll_debug_init()
1229 td->debugfs_dir, td, &attr_registers_fops)) in dfll_debug_init()
1235 debugfs_remove_recursive(td->debugfs_dir); in dfll_debug_init()
1253 static void dfll_set_default_params(struct tegra_dfll *td) in dfll_set_default_params() argument
1257 val = DIV_ROUND_UP(td->ref_rate, td->sample_rate * 32); in dfll_set_default_params()
1259 dfll_writel(td, val, DFLL_CONFIG); in dfll_set_default_params()
1261 val = (td->force_mode << DFLL_PARAMS_FORCE_MODE_SHIFT) | in dfll_set_default_params()
1262 (td->cf << DFLL_PARAMS_CF_PARAM_SHIFT) | in dfll_set_default_params()
1263 (td->ci << DFLL_PARAMS_CI_PARAM_SHIFT) | in dfll_set_default_params()
1264 (td->cg << DFLL_PARAMS_CG_PARAM_SHIFT) | in dfll_set_default_params()
1265 (td->cg_scale ? DFLL_PARAMS_CG_SCALE : 0); in dfll_set_default_params()
1266 dfll_writel(td, val, DFLL_PARAMS); in dfll_set_default_params()
1268 dfll_tune_low(td); in dfll_set_default_params()
1269 dfll_writel(td, td->droop_ctrl, DFLL_DROOP_CTRL); in dfll_set_default_params()
1270 dfll_writel(td, DFLL_MONITOR_CTRL_FREQ, DFLL_MONITOR_CTRL); in dfll_set_default_params()
1281 static int dfll_init_clks(struct tegra_dfll *td) in dfll_init_clks() argument
1283 td->ref_clk = devm_clk_get(td->dev, "ref"); in dfll_init_clks()
1284 if (IS_ERR(td->ref_clk)) { in dfll_init_clks()
1285 dev_err(td->dev, "missing ref clock\n"); in dfll_init_clks()
1286 return PTR_ERR(td->ref_clk); in dfll_init_clks()
1289 td->soc_clk = devm_clk_get(td->dev, "soc"); in dfll_init_clks()
1290 if (IS_ERR(td->soc_clk)) { in dfll_init_clks()
1291 dev_err(td->dev, "missing soc clock\n"); in dfll_init_clks()
1292 return PTR_ERR(td->soc_clk); in dfll_init_clks()
1295 td->i2c_clk = devm_clk_get(td->dev, "i2c"); in dfll_init_clks()
1296 if (IS_ERR(td->i2c_clk)) { in dfll_init_clks()
1297 dev_err(td->dev, "missing i2c clock\n"); in dfll_init_clks()
1298 return PTR_ERR(td->i2c_clk); in dfll_init_clks()
1300 td->i2c_clk_rate = clk_get_rate(td->i2c_clk); in dfll_init_clks()
1314 static int dfll_init(struct tegra_dfll *td) in dfll_init() argument
1318 td->ref_rate = clk_get_rate(td->ref_clk); in dfll_init()
1319 if (td->ref_rate != REF_CLOCK_RATE) { in dfll_init()
1320 dev_err(td->dev, "unexpected ref clk rate %lu, expecting %lu", in dfll_init()
1321 td->ref_rate, REF_CLOCK_RATE); in dfll_init()
1325 reset_control_deassert(td->dvco_rst); in dfll_init()
1327 ret = clk_prepare(td->ref_clk); in dfll_init()
1329 dev_err(td->dev, "failed to prepare ref_clk\n"); in dfll_init()
1333 ret = clk_prepare(td->soc_clk); in dfll_init()
1335 dev_err(td->dev, "failed to prepare soc_clk\n"); in dfll_init()
1339 ret = clk_prepare(td->i2c_clk); in dfll_init()
1341 dev_err(td->dev, "failed to prepare i2c_clk\n"); in dfll_init()
1345 td->last_unrounded_rate = 0; in dfll_init()
1347 pm_runtime_enable(td->dev); in dfll_init()
1348 pm_runtime_get_sync(td->dev); in dfll_init()
1350 dfll_set_mode(td, DFLL_DISABLED); in dfll_init()
1351 dfll_set_default_params(td); in dfll_init()
1353 if (td->soc->init_clock_trimmers) in dfll_init()
1354 td->soc->init_clock_trimmers(); in dfll_init()
1356 dfll_set_open_loop_config(td); in dfll_init()
1358 dfll_init_out_if(td); in dfll_init()
1360 pm_runtime_put_sync(td->dev); in dfll_init()
1365 clk_unprepare(td->soc_clk); in dfll_init()
1367 clk_unprepare(td->ref_clk); in dfll_init()
1369 reset_control_assert(td->dvco_rst); in dfll_init()
1382 static int find_vdd_map_entry_exact(struct tegra_dfll *td, int uV) in find_vdd_map_entry_exact() argument
1386 n_voltages = regulator_count_voltages(td->vdd_reg); in find_vdd_map_entry_exact()
1388 reg_uV = regulator_list_voltage(td->vdd_reg, i); in find_vdd_map_entry_exact()
1396 dev_err(td->dev, "no voltage map entry for %d uV\n", uV); in find_vdd_map_entry_exact()
1404 static int find_vdd_map_entry_min(struct tegra_dfll *td, int uV) in find_vdd_map_entry_min() argument
1408 n_voltages = regulator_count_voltages(td->vdd_reg); in find_vdd_map_entry_min()
1410 reg_uV = regulator_list_voltage(td->vdd_reg, i); in find_vdd_map_entry_min()
1418 dev_err(td->dev, "no voltage map entry rounding to %d uV\n", uV); in find_vdd_map_entry_min()
1434 static int dfll_build_i2c_lut(struct tegra_dfll *td) in dfll_build_i2c_lut() argument
1446 opp = dev_pm_opp_find_freq_floor(td->soc->dev, &rate); in dfll_build_i2c_lut()
1448 dev_err(td->dev, "couldn't get vmax opp, empty opp table?\n"); in dfll_build_i2c_lut()
1453 v = td->soc->min_millivolts * 1000; in dfll_build_i2c_lut()
1454 lut = find_vdd_map_entry_exact(td, v); in dfll_build_i2c_lut()
1457 td->i2c_lut[0] = lut; in dfll_build_i2c_lut()
1460 opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate); in dfll_build_i2c_lut()
1465 if (v_opp <= td->soc->min_millivolts * 1000) in dfll_build_i2c_lut()
1466 td->dvco_rate_min = dev_pm_opp_get_freq(opp); in dfll_build_i2c_lut()
1473 selector = find_vdd_map_entry_min(td, v); in dfll_build_i2c_lut()
1476 if (selector != td->i2c_lut[j - 1]) in dfll_build_i2c_lut()
1477 td->i2c_lut[j++] = selector; in dfll_build_i2c_lut()
1481 selector = find_vdd_map_entry_exact(td, v); in dfll_build_i2c_lut()
1484 if (selector != td->i2c_lut[j - 1]) in dfll_build_i2c_lut()
1485 td->i2c_lut[j++] = selector; in dfll_build_i2c_lut()
1490 td->i2c_lut_size = j; in dfll_build_i2c_lut()
1492 if (!td->dvco_rate_min) in dfll_build_i2c_lut()
1493 dev_err(td->dev, "no opp above DFLL minimum voltage %d mV\n", in dfll_build_i2c_lut()
1494 td->soc->min_millivolts); in dfll_build_i2c_lut()
1514 static bool read_dt_param(struct tegra_dfll *td, const char *param, u32 *dest) in read_dt_param() argument
1516 int err = of_property_read_u32(td->dev->of_node, param, dest); in read_dt_param()
1519 dev_err(td->dev, "failed to read DT parameter %s: %d\n", in read_dt_param()
1535 static int dfll_fetch_i2c_params(struct tegra_dfll *td) in dfll_fetch_i2c_params() argument
1543 if (!read_dt_param(td, "nvidia,i2c-fs-rate", &td->i2c_fs_rate)) in dfll_fetch_i2c_params()
1546 regmap = regulator_get_regmap(td->vdd_reg); in dfll_fetch_i2c_params()
1550 td->i2c_slave_addr = i2c_client->addr; in dfll_fetch_i2c_params()
1552 ret = regulator_get_hardware_vsel_register(td->vdd_reg, in dfll_fetch_i2c_params()
1556 dev_err(td->dev, in dfll_fetch_i2c_params()
1560 td->i2c_reg = vsel_reg; in dfll_fetch_i2c_params()
1562 ret = dfll_build_i2c_lut(td); in dfll_fetch_i2c_params()
1564 dev_err(td->dev, "couldn't build I2C LUT\n"); in dfll_fetch_i2c_params()
1578 static int dfll_fetch_common_params(struct tegra_dfll *td) in dfll_fetch_common_params() argument
1582 ok &= read_dt_param(td, "nvidia,droop-ctrl", &td->droop_ctrl); in dfll_fetch_common_params()
1583 ok &= read_dt_param(td, "nvidia,sample-rate", &td->sample_rate); in dfll_fetch_common_params()
1584 ok &= read_dt_param(td, "nvidia,force-mode", &td->force_mode); in dfll_fetch_common_params()
1585 ok &= read_dt_param(td, "nvidia,cf", &td->cf); in dfll_fetch_common_params()
1586 ok &= read_dt_param(td, "nvidia,ci", &td->ci); in dfll_fetch_common_params()
1587 ok &= read_dt_param(td, "nvidia,cg", &td->cg); in dfll_fetch_common_params()
1588 td->cg_scale = of_property_read_bool(td->dev->of_node, in dfll_fetch_common_params()
1591 if (of_property_read_string(td->dev->of_node, "clock-output-names", in dfll_fetch_common_params()
1592 &td->output_clock_name)) { in dfll_fetch_common_params()
1593 dev_err(td->dev, "missing clock-output-names property\n"); in dfll_fetch_common_params()
1617 struct tegra_dfll *td; in tegra_dfll_register() local
1625 td = devm_kzalloc(&pdev->dev, sizeof(*td), GFP_KERNEL); in tegra_dfll_register()
1626 if (!td) in tegra_dfll_register()
1628 td->dev = &pdev->dev; in tegra_dfll_register()
1629 platform_set_drvdata(pdev, td); in tegra_dfll_register()
1631 td->soc = soc; in tegra_dfll_register()
1633 td->vdd_reg = devm_regulator_get(td->dev, "vdd-cpu"); in tegra_dfll_register()
1634 if (IS_ERR(td->vdd_reg)) { in tegra_dfll_register()
1635 dev_err(td->dev, "couldn't get vdd_cpu regulator\n"); in tegra_dfll_register()
1636 return PTR_ERR(td->vdd_reg); in tegra_dfll_register()
1639 td->dvco_rst = devm_reset_control_get(td->dev, "dvco"); in tegra_dfll_register()
1640 if (IS_ERR(td->dvco_rst)) { in tegra_dfll_register()
1641 dev_err(td->dev, "couldn't get dvco reset\n"); in tegra_dfll_register()
1642 return PTR_ERR(td->dvco_rst); in tegra_dfll_register()
1645 ret = dfll_fetch_common_params(td); in tegra_dfll_register()
1647 dev_err(td->dev, "couldn't parse device tree parameters\n"); in tegra_dfll_register()
1651 ret = dfll_fetch_i2c_params(td); in tegra_dfll_register()
1657 dev_err(td->dev, "no control register resource\n"); in tegra_dfll_register()
1661 td->base = devm_ioremap(td->dev, mem->start, resource_size(mem)); in tegra_dfll_register()
1662 if (!td->base) { in tegra_dfll_register()
1663 dev_err(td->dev, "couldn't ioremap DFLL control registers\n"); in tegra_dfll_register()
1669 dev_err(td->dev, "no i2c_base resource\n"); in tegra_dfll_register()
1673 td->i2c_base = devm_ioremap(td->dev, mem->start, resource_size(mem)); in tegra_dfll_register()
1674 if (!td->i2c_base) { in tegra_dfll_register()
1675 dev_err(td->dev, "couldn't ioremap i2c_base resource\n"); in tegra_dfll_register()
1681 dev_err(td->dev, "no i2c_controller_base resource\n"); in tegra_dfll_register()
1685 td->i2c_controller_base = devm_ioremap(td->dev, mem->start, in tegra_dfll_register()
1687 if (!td->i2c_controller_base) { in tegra_dfll_register()
1688 dev_err(td->dev, in tegra_dfll_register()
1695 dev_err(td->dev, "no lut_base resource\n"); in tegra_dfll_register()
1699 td->lut_base = devm_ioremap(td->dev, mem->start, resource_size(mem)); in tegra_dfll_register()
1700 if (!td->lut_base) { in tegra_dfll_register()
1701 dev_err(td->dev, in tegra_dfll_register()
1706 ret = dfll_init_clks(td); in tegra_dfll_register()
1713 ret = dfll_init(td); in tegra_dfll_register()
1717 ret = dfll_register_clk(td); in tegra_dfll_register()
1724 dfll_debug_init(td); in tegra_dfll_register()
1741 struct tegra_dfll *td = platform_get_drvdata(pdev); in tegra_dfll_unregister() local
1744 if (td->mode != DFLL_DISABLED) { in tegra_dfll_unregister()
1750 debugfs_remove_recursive(td->debugfs_dir); in tegra_dfll_unregister()
1752 dfll_unregister_clk(td); in tegra_dfll_unregister()
1755 clk_unprepare(td->ref_clk); in tegra_dfll_unregister()
1756 clk_unprepare(td->soc_clk); in tegra_dfll_unregister()
1757 clk_unprepare(td->i2c_clk); in tegra_dfll_unregister()
1759 reset_control_assert(td->dvco_rst); in tegra_dfll_unregister()