387 		dev_err(dev, "could not enable ref clock: %d\n", ret);  in tegra_dfll_runtime_resume()
393 		dev_err(dev, "could not enable register clock: %d\n", ret);  in tegra_dfll_runtime_resume()
400 		dev_err(dev, "could not enable i2c clock: %d\n", ret);  in tegra_dfll_runtime_resume()
684 			dev_err(td->dev, "%s: Rate %lu is too low\n",  in dfll_calculate_rate_request()
695 		dev_err(td->dev, "%s: Rate %lu is above dfll range\n",  in dfll_calculate_rate_request()
756 		dev_err(td->dev, "%s: Cannot set DFLL rate in %s mode\n",  in dfll_request_rate()
788 		dev_err(td->dev, "cannot disable DFLL in %s mode\n",  in dfll_disable()
809 		dev_err(td->dev, "cannot enable DFLL in %s mode\n",  in dfll_enable()
864 			dev_err(td->dev, "%s: Cannot lock DFLL at rate 0\n",  in dfll_lock()
876 		dev_err(td->dev, "%s: Cannot lock DFLL in %s mode\n",  in dfll_lock()
903 		dev_err(td->dev, "%s: Cannot unlock DFLL in %s mode\n",  in dfll_unlock()
1020 		dev_err(td->dev, "DFLL clock registration error\n");  in dfll_register_clk()
1027 		dev_err(td->dev, "of_clk_add_provider() failed\n");  in dfll_register_clk()
1285 		dev_err(td->dev, "missing ref clock\n");  in dfll_init_clks()
1291 		dev_err(td->dev, "missing soc clock\n");  in dfll_init_clks()
1297 		dev_err(td->dev, "missing i2c clock\n");  in dfll_init_clks()
1320 		dev_err(td->dev, "unexpected ref clk rate %lu, expecting %lu",  in dfll_init()
1329 		dev_err(td->dev, "failed to prepare ref_clk\n");  in dfll_init()
1335 		dev_err(td->dev, "failed to prepare soc_clk\n");  in dfll_init()
1341 		dev_err(td->dev, "failed to prepare i2c_clk\n");  in dfll_init()
1396 	dev_err(td->dev, "no voltage map entry for %d uV\n", uV);  in find_vdd_map_entry_exact()
1418 	dev_err(td->dev, "no voltage map entry rounding to %d uV\n", uV);  in find_vdd_map_entry_min()
1448 		dev_err(td->dev, "couldn't get vmax opp, empty opp table?\n");  in dfll_build_i2c_lut()
1493 		dev_err(td->dev, "no opp above DFLL minimum voltage %d mV\n",  in dfll_build_i2c_lut()
1519 		dev_err(td->dev, "failed to read DT parameter %s: %d\n",  in read_dt_param()
1556 		dev_err(td->dev,  in dfll_fetch_i2c_params()
1564 		dev_err(td->dev, "couldn't build I2C LUT\n");  in dfll_fetch_i2c_params()
1593 		dev_err(td->dev, "missing clock-output-names property\n");  in dfll_fetch_common_params()
1621 		dev_err(&pdev->dev, "no tegra_dfll_soc_data provided\n");  in tegra_dfll_register()
1635 		dev_err(td->dev, "couldn't get vdd_cpu regulator\n");  in tegra_dfll_register()
1641 		dev_err(td->dev, "couldn't get dvco reset\n");  in tegra_dfll_register()
1647 		dev_err(td->dev, "couldn't parse device tree parameters\n");  in tegra_dfll_register()
1657 		dev_err(td->dev, "no control register resource\n");  in tegra_dfll_register()
1663 		dev_err(td->dev, "couldn't ioremap DFLL control registers\n");  in tegra_dfll_register()
1669 		dev_err(td->dev, "no i2c_base resource\n");  in tegra_dfll_register()
1675 		dev_err(td->dev, "couldn't ioremap i2c_base resource\n");  in tegra_dfll_register()
1681 		dev_err(td->dev, "no i2c_controller_base resource\n");  in tegra_dfll_register()
1688 		dev_err(td->dev,  in tegra_dfll_register()
1695 		dev_err(td->dev, "no lut_base resource\n");  in tegra_dfll_register()
1701 		dev_err(td->dev,  in tegra_dfll_register()
1708 		dev_err(&pdev->dev, "DFLL clock init error\n");  in tegra_dfll_register()
1719 		dev_err(&pdev->dev, "DFLL clk registration failed\n");  in tegra_dfll_register()
1745 		dev_err(&pdev->dev,  in tegra_dfll_unregister()